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TMS320C5515

現行

低功率 C55x 定點 DSP - 高達 120MHz、USB、LDC 介面、FFT HWA、SAR ADC

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產品規格表

TMS320C5515

現行
立即訂購

產品詳細資料

CPU 16-bit Frequency (MHz) 100, 240 Hardware accelerators FFT Coprocessor Operating system DSP/BIOS, VLX Rating Catalog Operating temperature range (°C) -40 to 85
CPU 16-bit Frequency (MHz) 100, 240 Hardware accelerators FFT Coprocessor Operating system DSP/BIOS, VLX Rating Catalog Operating temperature range (°C) -40 to 85
NFBGA (ZCH) 196 100 mm² (10 mm × 10 mm)
  • High-Performance, Low-Power, TMS320C55x™ Fixed-Point Digital Signal Processor
    • 16.67-, 13.33-, 10-, 8.33-ns Instruction Cycle Time
    • 60-, 75-, 100-, 120-MHz Clock Rate
    • One/Two Instructions Executed per Cycle
    • Dual Multipliers [Up to 200 or 240 Million Multiply-Accumulates per Second (MMACS)]
    • Two Arithmetic/Logic Units (ALUs)
    • Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses
    • Software-Compatible With C55x Devices
    • Industrial Temperature Devices Available
  • 320K Bytes Zero-Wait State On-Chip RAM, Composed of:
    • 64K Bytes of Dual-Access RAM (DARAM), 8 Blocks of 4K x 16-Bit
    • 256K Bytes of Single-Access RAM (SARAM), 32 Blocks of 4K x 16-Bit
  • 128K Bytes of Zero Wait-State On-Chip ROM
    (4 Blocks of 16K x 16-Bit)
  • 4M x 16-Bit Maximum Addressable External Memory Space (SDRAM/mSDRAM)
  • 16-/8-Bit External Memory Interface (EMIF) with Glueless Interface to:
    • 8-/16-Bit NAND Flash, 1- and 4-Bit ECC
    • 8-/16-Bit NOR Flash
    • Asynchronous Static RAM (SRAM)
    • SDRAM/mSDRAM (1.8-, 2.5-, 2.75-, and 3.3-V)
  • Direct Memory Access (DMA) Controller
    • Four DMA With 4 Channels Each (16-Channels Total)
  • Three 32-Bit General-Purpose Timers
    • One Selectable as a Watchdog and/or GP
  • Two MultiMedia Card/Secure Digital (MMC/SD) Interfaces
  • Universal Asynchronous Receiver/Transmitter (UART)
  • Serial-Port Interface (SPI) With Four Chip-Selects
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Four Inter-IC Sound (I2S Bus™) for Data Transport
  • Device USB Port With Integrated 2.0 High-Speed PHY that Supports:
    • USB 2.0 Full- and High-Speed Device
  • LCD Bridge With Asynchronous Interface
  • Tightly-Coupled FFT Hardware Accelerator
  • 10-Bit 4-Input Successive Approximation (SAR) ADC
  • Real-Time Clock (RTC) With Crystal Input, With Separate Clock Domain and Power Supply
  • Four Core Isolated Power Supply Domains: Analog, RTC, CPU and Peripherals, and USB
  • Four I/O Isolated Power Supply Domains: RTC I/O, EMIF I/O, USB PHY, and DVDDIO
  • Three integrated LDOs (DSP_LDO, ANA_LDO, and USB_LDO) to power the isolated domains: DSP Core, Analog, and USB Core, respectively
  • Low-Power S/W Programmable Phase-Locked Loop (PLL) Clock Generator
  • On-Chip ROM Bootloader (RBL) to Boot From NAND Flash, NOR Flash, SPI EEPROM, SPI Serial Flash or I2C EEPROM
  • IEEE-1149.1 (JTAG)
    Boundary-Scan-Compatible
  • Up to 26 General-Purpose I/O (GPIO) Pins
    (Multiplexed With Other Device Functions)
  • 196-Terminal Pb-Free Plastic BGA (Ball Grid Array) (ZCH Suffix)
  • 1.05-V Core (60 or 75 MHz), 1.8-V, 2.5-V, 2.75-V, or 3.3-V I/Os
  • 1.3-V Core (100, 120 MHz), 1.8-V, 2.5-V, 2.75-V, or 3.3-V I/Os

All trademarks are the property of their respective owners. All trademarks are the property of their respective owners.

  • High-Performance, Low-Power, TMS320C55x™ Fixed-Point Digital Signal Processor
    • 16.67-, 13.33-, 10-, 8.33-ns Instruction Cycle Time
    • 60-, 75-, 100-, 120-MHz Clock Rate
    • One/Two Instructions Executed per Cycle
    • Dual Multipliers [Up to 200 or 240 Million Multiply-Accumulates per Second (MMACS)]
    • Two Arithmetic/Logic Units (ALUs)
    • Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses
    • Software-Compatible With C55x Devices
    • Industrial Temperature Devices Available
  • 320K Bytes Zero-Wait State On-Chip RAM, Composed of:
    • 64K Bytes of Dual-Access RAM (DARAM), 8 Blocks of 4K x 16-Bit
    • 256K Bytes of Single-Access RAM (SARAM), 32 Blocks of 4K x 16-Bit
  • 128K Bytes of Zero Wait-State On-Chip ROM
    (4 Blocks of 16K x 16-Bit)
  • 4M x 16-Bit Maximum Addressable External Memory Space (SDRAM/mSDRAM)
  • 16-/8-Bit External Memory Interface (EMIF) with Glueless Interface to:
    • 8-/16-Bit NAND Flash, 1- and 4-Bit ECC
    • 8-/16-Bit NOR Flash
    • Asynchronous Static RAM (SRAM)
    • SDRAM/mSDRAM (1.8-, 2.5-, 2.75-, and 3.3-V)
  • Direct Memory Access (DMA) Controller
    • Four DMA With 4 Channels Each (16-Channels Total)
  • Three 32-Bit General-Purpose Timers
    • One Selectable as a Watchdog and/or GP
  • Two MultiMedia Card/Secure Digital (MMC/SD) Interfaces
  • Universal Asynchronous Receiver/Transmitter (UART)
  • Serial-Port Interface (SPI) With Four Chip-Selects
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Four Inter-IC Sound (I2S Bus™) for Data Transport
  • Device USB Port With Integrated 2.0 High-Speed PHY that Supports:
    • USB 2.0 Full- and High-Speed Device
  • LCD Bridge With Asynchronous Interface
  • Tightly-Coupled FFT Hardware Accelerator
  • 10-Bit 4-Input Successive Approximation (SAR) ADC
  • Real-Time Clock (RTC) With Crystal Input, With Separate Clock Domain and Power Supply
  • Four Core Isolated Power Supply Domains: Analog, RTC, CPU and Peripherals, and USB
  • Four I/O Isolated Power Supply Domains: RTC I/O, EMIF I/O, USB PHY, and DVDDIO
  • Three integrated LDOs (DSP_LDO, ANA_LDO, and USB_LDO) to power the isolated domains: DSP Core, Analog, and USB Core, respectively
  • Low-Power S/W Programmable Phase-Locked Loop (PLL) Clock Generator
  • On-Chip ROM Bootloader (RBL) to Boot From NAND Flash, NOR Flash, SPI EEPROM, SPI Serial Flash or I2C EEPROM
  • IEEE-1149.1 (JTAG)
    Boundary-Scan-Compatible
  • Up to 26 General-Purpose I/O (GPIO) Pins
    (Multiplexed With Other Device Functions)
  • 196-Terminal Pb-Free Plastic BGA (Ball Grid Array) (ZCH Suffix)
  • 1.05-V Core (60 or 75 MHz), 1.8-V, 2.5-V, 2.75-V, or 3.3-V I/Os
  • 1.3-V Core (100, 120 MHz), 1.8-V, 2.5-V, 2.75-V, or 3.3-V I/Os

All trademarks are the property of their respective owners. All trademarks are the property of their respective owners.

The device is a member of TI's TMS320C5000™ fixed-point Digital Signal Processor (DSP) product family and is designed for low-power applications.

The fixed-point DSP is based on the TMS320C55x™ DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with 4 channels, providing data movement for 16-independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.

The C55x CPU supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to the Address Unit (AU) and Data Unit (DU) resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.

The general-purpose input and output functions along with the 10-bit SAR ADC provide sufficient pins for status, interrupts, and bit I/O for LCD displays, keyboards, and media interfaces. Serial media is supported through two MultiMedia Card/Secure Digital (MMC/SD) peripherals, four Inter-IC Sound (I2S Bus™) modules, one Serial-Port Interface (SPI) with up to 4 chip selects, one I2C multi-master and slave interface, and a Universal Asynchronous Receiver/Transmitter (UART) interface.

The device peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM, NOR, NAND, and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM (SDRAM) and mobile SDRAM (mSDRAM). Additional peripherals include: a high-speed Universal Serial Bus (USB2.0) device mode only, and a real-time clock (RTC). This device also includes three general-purpose timers with one configurable as a watchdog timer, and an analog phase-locked loop (APLL) clock generator.

In addition, the device includes a tightly-coupled FFT Hardware Accelerator. The tightly-coupled FFT Hardware Accelerator supports 8 to 1024-point (in power of 2) real and complex-valued FFTs.

Furthermore, the device includes three integrated LDOs (DSP_LDO, ANA_LDO, and USB_LDO) to power different sections of the device. The DSP_LDO can provide 1.3 V or 1.05 V to the DSP core (CVDD), selectable on-the-fly by software as long as operating frequency ranges are observed. To allow for lowest power operation, the programmer can shutdown the internal DSP_LDO cutting power to the DSP core (CVDD) while an external supply provides power to the RTC (CVDDRTC and DVDDRTC). The ANA_LDO is designed to provide 1.3 V to the DSP PLL (VDDA_PLL), SAR, and power management circuits (VDDA_ANA). The USB_LDO provides 1.3 V to USB core digital (USB_VDD1P3) and PHY circuits (USB_VDDA1P3). The RTC alarm interrupt or the WAKEUP pin can re-enable the internal DSP_LDO and re-apply power to the DSP core.

The device is supported by the industry’s award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments’ algorithm standard, and the industry’s largest third-party network. Code Composer Studio IDE features code generation tools including a C Compiler and Linker, RTDX™, XDS100™, XDS510™, XDS560™ emulation device drivers, and evaluation modules. The device is also supported by the C55x DSP Library which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip support libraries.

The device is a member of TI's TMS320C5000™ fixed-point Digital Signal Processor (DSP) product family and is designed for low-power applications.

The fixed-point DSP is based on the TMS320C55x™ DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with 4 channels, providing data movement for 16-independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.

The C55x CPU supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to the Address Unit (AU) and Data Unit (DU) resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.

The general-purpose input and output functions along with the 10-bit SAR ADC provide sufficient pins for status, interrupts, and bit I/O for LCD displays, keyboards, and media interfaces. Serial media is supported through two MultiMedia Card/Secure Digital (MMC/SD) peripherals, four Inter-IC Sound (I2S Bus™) modules, one Serial-Port Interface (SPI) with up to 4 chip selects, one I2C multi-master and slave interface, and a Universal Asynchronous Receiver/Transmitter (UART) interface.

The device peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM, NOR, NAND, and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM (SDRAM) and mobile SDRAM (mSDRAM). Additional peripherals include: a high-speed Universal Serial Bus (USB2.0) device mode only, and a real-time clock (RTC). This device also includes three general-purpose timers with one configurable as a watchdog timer, and an analog phase-locked loop (APLL) clock generator.

In addition, the device includes a tightly-coupled FFT Hardware Accelerator. The tightly-coupled FFT Hardware Accelerator supports 8 to 1024-point (in power of 2) real and complex-valued FFTs.

Furthermore, the device includes three integrated LDOs (DSP_LDO, ANA_LDO, and USB_LDO) to power different sections of the device. The DSP_LDO can provide 1.3 V or 1.05 V to the DSP core (CVDD), selectable on-the-fly by software as long as operating frequency ranges are observed. To allow for lowest power operation, the programmer can shutdown the internal DSP_LDO cutting power to the DSP core (CVDD) while an external supply provides power to the RTC (CVDDRTC and DVDDRTC). The ANA_LDO is designed to provide 1.3 V to the DSP PLL (VDDA_PLL), SAR, and power management circuits (VDDA_ANA). The USB_LDO provides 1.3 V to USB core digital (USB_VDD1P3) and PHY circuits (USB_VDDA1P3). The RTC alarm interrupt or the WAKEUP pin can re-enable the internal DSP_LDO and re-apply power to the DSP core.

The device is supported by the industry’s award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments’ algorithm standard, and the industry’s largest third-party network. Code Composer Studio IDE features code generation tools including a C Compiler and Linker, RTDX™, XDS100™, XDS510™, XDS560™ emulation device drivers, and evaluation modules. The device is also supported by the C55x DSP Library which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip support libraries.
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技術文件

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 TMS320C5515 Fixed-Point Digital Signal Processor datasheet (Rev. F) 2013/10/21
* 勘誤表 TMS320C5515/C5514 Fixed-Point DSP Silicon Errata (Silicon Revision 2.0) (Rev. D) 2015/7/15
應用說明 How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A) PDF | HTML 2021/5/19
應用說明 Using the TMS320C5515/14/05/04 Bootloader (Rev. D) 2019/11/25
應用說明 TMS320C5505/15/35/45 schematic checklist PDF | HTML 2019/2/14
應用說明 MEMS Microphone Direct PDM Input via I2S to a C5515 EVM With Software Decimation 2016/9/22
應用說明 Usage Guidelines for C55x On-Chip Low Dropout Regulators (LDOs) 2016/7/26
應用說明 Power Estimation and Pwr Consumption Sum for TMS320C5504/05/14/15/32/33/34/35/45 (Rev. A) 2016/4/4
應用說明 Instructions to Benchmark C55 DSP Library 2016/4/1
應用說明 C5000 DSP-Based Low-Power System Design 2015/11/30
使用指南 TMS320C5515/14/05/04/VC05/VC04 DSP MMC/SD Card Controller User's Guide (Rev. B) 2015/9/30
應用說明 Migrating from TMS320C5515 to 5517 2014/4/2
使用指南 TMS320C5515/14/05/04 DSP Universal Serial Bus 2.0 (USB) Controller User's Guide (Rev. A) 2013/10/3
應用說明 FFT Implementation on the TMS320VC5505, TMS320C5505, and TMS320C5515 DSPs (Rev. B) 2013/1/9
使用指南 TMS320C5515/14/05/04 DSP External Memory Interface (EMIF) User's Guide (Rev. B) 2012/11/18
使用指南 TMS320C5515/14/05/04 DSP Real-Time Clock (RTC) User's Guide (Rev. A) 2012/11/15
使用指南 TMS320C5515 DSP System User's Guide (Rev. E) 2012/9/14
使用指南 TMS320C5515/14/05/04 DSP Inter-IC Sound (I2S) Bus User's Guide (Rev. B) 2012/8/9
使用指南 TMS320C5515/14/05/04 DSP Direct Memory Access (DMA) Controller User's Guide (Rev. A) 2012/3/7
使用指南 TMS320C5515/05/VC05 DSP Successive Approx. Register (SAR) ADC User's Guide (Rev. C) 2012/1/13
應用說明 Migrating from TMS320C5515/05 to TMS320C5535/34/33/32 (Rev. A) 2011/12/22
使用指南 TMS320C55x DSP Peripherals Overview Reference Guide (Rev. K) 2011/12/15
使用指南 TMS320C55x Optimizing C/C++ Compiler User's Guide (Rev. G) 2011/11/9
使用指南 TMS320C55x Assembly Language Tools User's Guide (Rev. I) 2011/11/9
Product overview C5515 eZdsp (Rev. A) 2010/11/8
Product overview TMS320C5514 and TMS320C5515 DSP Product Bulletin 2010/1/18
Product overview TMS320C5504, TMS320C5505, TMS320C5515 and TMS320C5514 Product Bulletin 2010/1/12
Product overview Low-power Signal Chain Solutions Based on C5515 DSP 2010/1/12
使用指南 TMS320C5515/05/VC05 DSP Liquid Crystal Display Controller User's Guide 2009/9/21
使用指南 TMS320C5515/14/05/04/VC05/VC04 DSP UART User's Guide 2009/9/21
使用指南 TMS320C5515/14/05/04/VC05/VC04 DSP Inter-Integrated Circuit (I2C) Peripheral UG (Rev. A) 2009/9/21
使用指南 TMS320C5515/14/05/04/VC05/VC04 DSP Timer/Watchdog Timer User's Guide 2009/9/21
使用指南 TMS320C5515/14/05/04/VC05/VC04 DSP Serial Peripheral Interface (SPI) UG 2009/9/21
使用指南 TMS320C5515/14/05/04/VC05/VC04 DSP General-Purpose Input/Output User's Guide 2009/9/21
使用指南 TMS320C55x v3.x DSP Algebraic Instruction Set Reference Guide (Rev. E) 2009/6/24
使用指南 TMS320C55x v3.x DSP Mnemonic Instruction Set Reference Guide (Rev. E) 2009/6/24
使用指南 TMS320C55x DSP v3.x CPU Reference Guide (Rev. E) 2009/6/17

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偵錯探測器

TMDSEMU200-U — XDS200 USB 偵錯探測器

XDS200 是為 TI 嵌入式裝置偵錯的偵錯探測器（模擬器）。對於大多數裝置，建議使用較新、成本較低的 XDS110 (www.ti.com/tool/TMDSEMU110-U)。XDS200 支援單一 Pod 中廣泛的標準（IEEE1149.1、IEEE1149.7、SWD）。所有 XDS 偵錯探針在所有配備嵌入式追蹤緩衝器 (ETB) 的 Arm® 與 DSP 處理器中均支援核心與系統追蹤。

XDS200 透過 TI 20 接腳連接器（配備適用 TI 14 接腳、Arm Cortex® 10 接腳和 Arm 20 接腳的多重轉接器）連接到目標電路板，並透過 USB2.0 高速 (...)

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XDS560v2 是 XDS560™ 系列偵錯探測器中性能最高的，且同時支援傳統 JTAG 標準 (IEEE1149.1) 與 cJTAG (IEEE1149.7)。  請注意，其不支援序列線偵錯 (SWD)。

所有 XDS 偵錯探測器均在所有配備嵌入式追蹤緩衝器 (ETB) 的 ARM 與 DSP 處理器中支援核心與系統追蹤。  對於針腳上的追蹤，則需要 XDS560v2 PRO TRACE。

XDS560v2 透過 MIPI HSPT 60 針腳接頭 (具有用於 TI 14 針腳、TI 20 針腳和 ARM 20 針腳的多轉接器) 連接到目標電路板，並透過 USB2.0 高速 (...)

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TMDSEMU560V2STM-UE — XDS560v2 System Trace USB 與乙太網路偵錯探測器

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

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偵錯探測器

LB-3P-TRACE32-DSP — 適用於數位訊號處理器 (DSP) 的 Lauterbach TRACE32 偵錯和追蹤系統

Lauterbach‘s TRACE32® tools are a suite of leading-edge hardware and software components that enables developers to analyze, optimize and certify all kinds of single- or multi-core Digital Signal processors (DSPs) which are a popular choice for audio and video processing as well as radar data (...)

從：Lauterbach GmbH
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應用軟體及架構

C55X-USBAUDIO — C55x USB Audio Class Framework

The TMS320C55x™ Connected Audio Framework provides a software framework which allows the C55x devices to operate as a USB Audio peripheral. In addition to providing this capability, the framework can be extended by users by the incorporation of audio processing algorithms in the record and (...)
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驅動程式或資料庫

SPRC100 — TMS320C55x DSP 函式庫 (DSPLIB)

DSP 函式庫 (DSPLIB) 是適用於 C55x DSP 平台的高階最佳化 DSP 函式模組集合。此原始程式碼函式庫包括用於一般訊號處理數學運算的 C 可呼叫函式 (ANSI-C 語言相容)，以及移植至 C55x DSP 的向量函式。特性部分列出的函式專門針對 C55x DSP 進行了最佳化。

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SPRC133 — TMS320C55x 晶片支援庫 (CSL) – 標准和低功耗

C55x 晶片支援函式庫 (CSL) 提供了應用程式編程介面 (API)，可用來設定與控制 DSP 晶片內建的週邊設備，以實現易用性、各種 C55x 裝置間的相容性以及硬體抽象。CSL 透過提供標準化和可移植性，可縮短開發時間。

  • C55x CSL (SPRC133)：特性部分列出的函式專門針對 TMS320C55x DSP 設計，包括 C5501、C5502、 C5509、C5509A、C5510 和 C5510A。
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(...)

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SPRC264 — TMS320C5000/6000 映像庫 (IMGLIB)

C5000 6000 影像處理庫 (IMGLIB) 是適合 C 程式設計工具的最佳化影像/影片處理函式庫。此函式庫包括 C 可呼叫通用影像/影片處理常式，這些常式通常用於運算密集型即時應用。相較於同等標準 ANSI C 語言程式碼，使用這些常式可以實現更高性能。IMGLIB 透過立即可用的 DSP 功能與原始程式碼，能夠大幅縮短應用程式開發時間。

查看基準測試：DSP 核心基準測試

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TELECOMLIB — 電信和媒體庫 - 用於 TMS320C64x+ 和 TMS320C55x 處理器的 FAXLIB、VoLIB 和 AEC/AER

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

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軟體轉碼器

C55XCODECS — 轉碼器 - 針對 C55x 裝置進行最佳化

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into audio and speech applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes (...)

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軟體轉碼器

ADT-3P-DSPVOIPCODECS — 適應性數位技術 DSP VOIP、語音和音訊轉碼器

Adaptive Digital is a developer of voice quality enhancement algorithms, and best-in-class acoustic echo cancellation software that work with TI DSPs. Adaptive Digital has extensive experience in the algorithm development, implementation, optimization and configuration tuning. They provide (...)
從：Adaptive Digital Technologies, Inc.
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軟體轉碼器

ALGOT-3P-DSPVOIPCODECS — Algotron C5000 DSP 電信和音訊轉碼器

Algotron provides C5000 DSP software modules for telecoms & audio. Examples are: modem data pumps, speech coders, signal generators & detectors for DTMF and caller ID. All modules feature simple yet flexible interfaces with full re-entrancy. They come with user's guides, example (...)

從：Algotron
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軟體轉碼器

DSPI-3P-DSPVOIPCODECS — DSP 創新：DSP VoIP 轉碼器

DSP Innovations is a supplier of C5000TM DSP-software and engineering services. Proprietary and standard vocoders from DSPINI have superior characteristics, operate in range from 300 bps up to 64 kbps and are used in: secure voice, software defined radio, wireless, VoIP, voice storage, and more. (...)

從：DSP Innovations
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模擬型號

C5515 ZCH BSDL Model

SPRM496.ZIP (5 KB) - BSDL 模型
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模擬型號

C5515 ZCH IBIS Model

SPRM497.ZIP (445 KB) - IBIS 模型
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
NFBGA (ZCH) 196 Ultra Librarian
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