產品詳細資料

CPU 8 Arm Cortex-A720AE Coprocessors 6 Arm Cortex-R52+ Hardware accelerators Deep learning accelerator, Depth and motion processing accelerator, Video decode accelerator, Video encode accelerator Operating system FreeRTOS, INTEGRITY, Linux, QNX, SafeRTOS, u-velOSity Security Cryptographic acceleration, Secure boot TI functional safety category Functional Safety-Compliant Rating Catalog Power supply solution TPS6594-Q1 Operating temperature range (°C) -40 to 125
CPU 8 Arm Cortex-A720AE Coprocessors 6 Arm Cortex-R52+ Hardware accelerators Deep learning accelerator, Depth and motion processing accelerator, Video decode accelerator, Video encode accelerator Operating system FreeRTOS, INTEGRITY, Linux, QNX, SafeRTOS, u-velOSity Security Cryptographic acceleration, Secure boot TI functional safety category Functional Safety-Compliant Rating Catalog Power supply solution TPS6594-Q1 Operating temperature range (°C) -40 to 125
FCBGA (ALF) 827 576 mm² 24 x 24

Processor cores:

  • Up-to Eight Arm Cortex-A720AE MPUs
    • Lockstep capable

Real-Time processing CPUs :

  • Up-to 6x Arm® Cortex®-R52+ (or 3x pairs in Lockstep)
    • Virtualization for multi-core processing

System/SOC CPUs:

  • 8x Dual Arm® Cortex®-M55 (Lockstep)

DSP / AI processing :

  • Up to 4x C7™ neural processing unit(NPU)
    • Up to 400 TOPS

Vision and video processing:

  • Up to 16 cameras
  • DMPAC: Dense Optical Flow, Stereo Disparity Engine
  • 4x CSI-2 RX interface, 1x CSI-2 TX output

GPU and display processing:

  • Imagination DXS Family GPU

Display subsystem:

  • eDP1.5/DP2.1
    • Multi-Stream Transport (up to 4 displays, up to 4K60fps)
  • 1x DSI CPHY-2.0/DPHY-2.1
    • Up to 4 lanes per port (muxed with CSI-TX)
  • DSS Controller:
    • 4 pipelines + 1 Writeback path, up to 4k60 per pipe

Networking subsystem:

  • NPAC (Network Processing Accelerator) specialized subsystem for Ethernet switching and packet transfer
  • Integrated Ethernet Switch
    • 8 external ports
    • 10base-T1S (OA3P 3-wire i/f) supported on all ports
    • MACSEC per port, supports line rate

Memory:

  • LPDDR4x/5/5x interface
    • In-line ECC
  • 1x UFS3.0
  • 1x eMMC5.1 HS200
  • 2x XSPI interface up to 400MBps

Security:

  • SHE/EVITA Full compliant HSM, ISO21434 compliant

Functional Safety:

Safety features:

  • Support for full ASIL D or mixed ASIL D / ASIL B with FFI

High-speed serial interfaces:

  • 2x PCIe up to 4L
    • Gen5 controller
    • Root complex or Endpoint
  • 1x USB3.2 (Gen 2)/eUSB2.0

Video acceleration:

  • H.264/H.265 Encode/Decode: 1.0GP/s encode or decode, up to 10b support

Serial interfaces:

  • Up to 170 General-Purpose Input/Output (GPIO) pin capability

TPS6594-Q1 Companion Power Management ICs (PMIC):

  • Functional Safety-Compliant support up to ASIL D/SIL 3
  • Flexible mapping to support different use cases

Processor cores:

  • Up-to Eight Arm Cortex-A720AE MPUs
    • Lockstep capable

Real-Time processing CPUs :

  • Up-to 6x Arm® Cortex®-R52+ (or 3x pairs in Lockstep)
    • Virtualization for multi-core processing

System/SOC CPUs:

  • 8x Dual Arm® Cortex®-M55 (Lockstep)

DSP / AI processing :

  • Up to 4x C7™ neural processing unit(NPU)
    • Up to 400 TOPS

Vision and video processing:

  • Up to 16 cameras
  • DMPAC: Dense Optical Flow, Stereo Disparity Engine
  • 4x CSI-2 RX interface, 1x CSI-2 TX output

GPU and display processing:

  • Imagination DXS Family GPU

Display subsystem:

  • eDP1.5/DP2.1
    • Multi-Stream Transport (up to 4 displays, up to 4K60fps)
  • 1x DSI CPHY-2.0/DPHY-2.1
    • Up to 4 lanes per port (muxed with CSI-TX)
  • DSS Controller:
    • 4 pipelines + 1 Writeback path, up to 4k60 per pipe

Networking subsystem:

  • NPAC (Network Processing Accelerator) specialized subsystem for Ethernet switching and packet transfer
  • Integrated Ethernet Switch
    • 8 external ports
    • 10base-T1S (OA3P 3-wire i/f) supported on all ports
    • MACSEC per port, supports line rate

Memory:

  • LPDDR4x/5/5x interface
    • In-line ECC
  • 1x UFS3.0
  • 1x eMMC5.1 HS200
  • 2x XSPI interface up to 400MBps

Security:

  • SHE/EVITA Full compliant HSM, ISO21434 compliant

Functional Safety:

Safety features:

  • Support for full ASIL D or mixed ASIL D / ASIL B with FFI

High-speed serial interfaces:

  • 2x PCIe up to 4L
    • Gen5 controller
    • Root complex or Endpoint
  • 1x USB3.2 (Gen 2)/eUSB2.0

Video acceleration:

  • H.264/H.265 Encode/Decode: 1.0GP/s encode or decode, up to 10b support

Serial interfaces:

  • Up to 170 General-Purpose Input/Output (GPIO) pin capability

TPS6594-Q1 Companion Power Management ICs (PMIC):

  • Functional Safety-Compliant support up to ASIL D/SIL 3
  • Flexible mapping to support different use cases

The TDA5 high-performance compute SoC family is designed to deliver safe and efficient edge AI performance, with capabilities of up to 1200 TOPS, with integrated C7™ NPU and chiplet-ready architecture. This enables seamless progression to L3 autonomous driving in software-defined vehicles, where conditional automation is possible in both urban and highway environments. Additionally, the TDA5 SoCs are well-suited for similar applications in industrial transportation, humanoid and industrial robots, and aerospace and defense with their advanced sensor processing, cybersecurity, and functional safety features.

The TDA5 SoCs feature multiple specialized subsystems, each tailored to address the growing demand for high-performance compute and cross-domain applications. These subsystems include dedicated processing cores and hardware acceleration for security, vision processing, edge AI, display rendering, and networking. By offloading these tasks, the SoCs’ MPU and MCU cores are freed up to focus on user application software. Furthermore, support for PCIe, Ethernet, and other automotive standard peripherals enables safe, secure, and high-speed data transfer between different components and systems.

Building on two decades of leadership in the automotive processor market, the TDA5 architecture is designed to provide a scalable and high-performance solution for a wide range of applications. As an evolution of the TDA4 family, software developed for TDA4 can be easily scaled to the TDA5 family, with minimal rework required. This allows for the reuse of software assets and enables the development of more complex and sophisticated applications. The TDA5 family’s unique combination of high-performance real-time and analytics cores, along with the latest C7™ NPU and next-generation accelerators for image signal processing, makes it an optimized solution for various camera, radar, sensor fusion, and AI applications.

The TDA5 family provides high-performance compute capabilities for both traditional computer vision and deep learning algorithms, with industry-leading power/performance ratios. The high level of system integration enables lower costs for advanced automotive platforms, supporting multiple sensor modalities in centralized ECUs, multiple sensor domains, or a centralized automotive computer. Key processing and acceleration cores include the latest-generation C7™ DSP with scalar and vector cores, dedicated deep learning acceleration, latest application and GPU cores for general compute, a vision and imaging subsystem, video codec, network packet processing accelerator, and Ethernet switch, as well as a dedicated security subsystem. These cores are carefully integrated into an SoC architecture designed from the ground up to support functional safety at a system level, ensuring the highest level of reliability and performance in safety-critical applications.

The TDA5 high-performance compute SoC family is designed to deliver safe and efficient edge AI performance, with capabilities of up to 1200 TOPS, with integrated C7™ NPU and chiplet-ready architecture. This enables seamless progression to L3 autonomous driving in software-defined vehicles, where conditional automation is possible in both urban and highway environments. Additionally, the TDA5 SoCs are well-suited for similar applications in industrial transportation, humanoid and industrial robots, and aerospace and defense with their advanced sensor processing, cybersecurity, and functional safety features.

The TDA5 SoCs feature multiple specialized subsystems, each tailored to address the growing demand for high-performance compute and cross-domain applications. These subsystems include dedicated processing cores and hardware acceleration for security, vision processing, edge AI, display rendering, and networking. By offloading these tasks, the SoCs’ MPU and MCU cores are freed up to focus on user application software. Furthermore, support for PCIe, Ethernet, and other automotive standard peripherals enables safe, secure, and high-speed data transfer between different components and systems.

Building on two decades of leadership in the automotive processor market, the TDA5 architecture is designed to provide a scalable and high-performance solution for a wide range of applications. As an evolution of the TDA4 family, software developed for TDA4 can be easily scaled to the TDA5 family, with minimal rework required. This allows for the reuse of software assets and enables the development of more complex and sophisticated applications. The TDA5 family’s unique combination of high-performance real-time and analytics cores, along with the latest C7™ NPU and next-generation accelerators for image signal processing, makes it an optimized solution for various camera, radar, sensor fusion, and AI applications.

The TDA5 family provides high-performance compute capabilities for both traditional computer vision and deep learning algorithms, with industry-leading power/performance ratios. The high level of system integration enables lower costs for advanced automotive platforms, supporting multiple sensor modalities in centralized ECUs, multiple sensor domains, or a centralized automotive computer. Key processing and acceleration cores include the latest-generation C7™ DSP with scalar and vector cores, dedicated deep learning acceleration, latest application and GPU cores for general compute, a vision and imaging subsystem, video codec, network packet processing accelerator, and Ethernet switch, as well as a dedicated security subsystem. These cores are carefully integrated into an SoC architecture designed from the ground up to support functional safety at a system level, ensuring the highest level of reliability and performance in safety-critical applications.

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* Data sheet TDA54x Jacinto™ Processors datasheet PDF | HTML 2025年 12月 9日
Technical article 為何可擴充的高性能 SoC 是自駕車的未來 PDF | HTML 2025年 12月 31日
Application brief Accelerating next-generation automotive designs with the TDA5 Virtualizer™ Development Kit PDF | HTML 2025年 12月 23日

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偵錯探測器

LB-3P-TRACE32-ARM — 適用於 Arm® 架構微控制器和處理器的 Lauterbach TRACE32® 偵錯和追蹤系統

Lauterbach 的 TRACE32® 工具是一套先進的軟硬體元件,可讓開發人員分析、最佳化及認證各種 Arm® 架構微控制器和處理器。全球知名的嵌入式系統和 SoC 偵錯和追蹤解決方案是完美的解決方案,適用於從早期的矽前 (pre-silicon) 開發,到產品認證和現場故障排除等所有開發階段。Lauterbach 工具的直覺模組化設計為工程師提供現今最高的可用性能,以及可隨需求變化而調整和成長的系統。藉由 TRACE32® 偵錯器,開發人員也可透過單一偵錯介面,同時偵錯和控制 SoC 中的任何 C28x/C29x/C6x/C7x DSP 核心及所有其他 Arm (...)

軟體開發套件 (SDK)

SNPS-3P-TDA5-VDK — 適用於 TDA5 駕駛輔助 SoC 的 Synopsys 虛擬開發套件

The TDA5 Virtualizer Development Kit (VDK), built with Synopsys Virtualizer™, enables software development on a register-accurate simulation of TDA5 drive assist SoCs. This creates an electronics digital twin of production systems to execute unmodified binaries of production software (SW) with (...)
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應用軟體及架構

SV-3P-FRONTVISION — FrontVision - STRADVISION 汽車感知軟體

FrontVision 利用前置攝影機的輸入來偵測道路上的各種元素,例如車輛、行人、車道、交通號誌和交通標誌。其能讓使用者開發不同等級的自主駕駛功能,範圍從 Euro GSR/NCAP 法規要求的基本 ADAS 功能,到 L2/L2+/L3 以上等級的自動駕駛功能。
從:Stradvision
應用軟體及架構

SV-3P-SURROUNDVISION — SurroundVision - STRADVISION 汽車感知軟體

SurroundVision 會偵測車輛周圍的各種物體,包括車輛、行人、停車格和路緣,以環景攝影機影像作為輸入。透過其高準度的預警輸出,使用者可開發安全功能,例如盲區監控系統和自動停車輔助功能,即使在條件嚴苛的情境下也能發揮作用。
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IDE、配置、編譯器或偵錯程式

CCSTUDIO Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize embedded applications. Code Composer Studio is available across Windows®, Linux® and macOS® platforms.

(...)

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IDE、配置、編譯器或偵錯程式

GHS-3P-MULTI-IDE — Green Hills Software MULTI Integrated Development Environment

The MULTI® development environment has been in use by thousands of developers for three decades and is the industry’s unrivaled integrated development environment to create, debug, and optimize C, C++ and Ada  code for production-focused applications.  It brings together (...)
作業系統 (OS)

GHS-3P-UVELOSITY — Green Hills Software u-velOSity Safety RTOS

The µ-velOSity™ Safety RTOS is the smallest of Green Hills Software's real-time operating systems and was designed especially for microcontrollers. It supports a wide range of TI processor families using the Arm® Cortex-M or Cortex-R cores as a main CPU or as a co-processors (...)
作業系統 (OS)

QNX-3P-NEUTRINO-RTOS — QNX Neutrino RTOS

QNX Neutrino® 即時作業系統 (RTOS) 是一款功能完整且穩固的 RTOS,專為實現適用於汽車、醫療、運輸、軍事和工業嵌入式系統的新一代產品而設計。微核心設計與模組化架構,能讓客戶以低整體擁有成本打造高度最佳化且可靠的系統。
作業系統 (OS)

WHIS-3P-SAFERTOS — WITTENSTEIN SAFERTOS 預先認證的安全 RTOS

SAFERTOS® 是專為嵌入式處理器設計的獨特即時作業系統。經 TÜV SÜD 預先認證,符合 IEC 61508 SIL3 與 ISO 26262 ASILD 標準。SAFERTOS® 是由 WHIS 專家團隊專為安全而打造,適用於全球重要安全應用。WHIS 與德州儀器的合作已經超過十年。在此期間,WHIS 已將 SAFERTOS® 移植至各種 TI 處理器,支援所有熱門核心,並可依要求提供其他架構。SAFERTOS® 專為您的特定處理器/編譯器組合量身打造,隨附完整的原始程式碼與設計保證包,可完全一目了然整個設計生命週期。許多 WHIS 客戶開始使用 FreeRTOS (...)
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EXLFR-3P-ESYNC-OTA — 適用於軟體定義車輛的 Excelfore esync OTA 無線更新

Experience the future of the connected SDV starting with full vehicle OTA from Excelfore. The standardized and structured eSync pipeline securely scales to reach all the ECUs and smart sensors in the car, with the flexibility to cover any in-vehicle network topology or system architecture.
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TDA54-SW Software package enabling development on TDA54

This folder contains the restricted software packages for TDA54 enabling software development.
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產品
汽車駕駛輔助 SoC
TDA54-Q1 適用於 ADAS 和軟體定義車輛中的進階 AI 搭載新一代 C7TM NPU 的進階 SoC
軟體
軟體開發套件 (SDK)
SNPS-3P-TDA5-VDK 適用於 TDA5 駕駛輔助 SoC 的 Synopsys 虛擬開發套件
支援軟體

VCTR-3P-MICROSAR — 適用於微控制器和高性能電腦 (HPC) 的 Vector MICROSAR AUTOSAR 軟體

MICROSAR 與 DaVinci 產品系列透過適用於微控制器與 HPC 的精密嵌入式軟體和強大開發工具,簡化 ECU 開發。有了先進的基礎架構軟體,您即可為 ECU 建立最佳基礎,並利用相關工具簡化所有相關開發作業。MICROSAR 嵌入式軟體是根據 AUTOSAR 經典和適應性等相關標準所開發。軟體也適合符合最高 ASIL D 之 ISO 26262 標準的安全相關應用。此外,智慧網路安全功能可保護控制單元免受未經授權的存取和竄改。Vector 涵蓋所有汽車與其他工業應用的使用案例。對於配備高性能電腦的軟體定義車輛 (SDV),其可提供現代車輛作業系統,以做為開放式模組化軟體生態系統。
封裝 針腳 CAD 符號、佔位空間與 3D 模型
FCBGA (ALF) 827 Ultra Librarian

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