首頁 邏輯和電壓轉換 正反器、鎖存器和暫存器 D 型正反器
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邏輯和電壓轉換
正反器、鎖存器和暫存器
D 型正反器

SN74LVC1G74

現行

具清除和預設功能的單路正緣觸發 D 類正反器

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產品規格表

SN74LVC1G74

現行
產品規格表 立即訂購

產品詳細資料

Number of channels 1 Technology family LVC Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 200 IOL (max) (mA) 32 IOH (max) (mA) -32 Supply current (max) (µA) 10 Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 125 Rating Catalog
Number of channels 1 Technology family LVC Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 200 IOL (max) (mA) 32 IOH (max) (mA) -32 Supply current (max) (µA) 10 Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 125 Rating Catalog
VSSOP (DCU) 8 6.2 mm² (2 mm × 3.1 mm) SSOP (DCT) 8 11.8 mm² (2.95 mm × 4 mm) X2SON (DQE) 8 1.4 mm² (1.4 mm × 1 mm) UQFN (RSE) 8 2.25 mm² (1.5 mm × 1.5 mm)
  • Available in the Texas Instruments NanoFree™ package
  • Supports 5-V VCC operation
  • Inputs accept voltages to 5.5-V
  • Supports down translation to VCC
  • Maximum tpd of 5.9-ns at 3.3-V
  • Low power consumption, 10-µA maximum ICC
  • ±24-mA output drive at 3.3-V
  • Typical VOLP (output ground bounce) < 0.8-V at VCC = 3.3-V, TA = 25°C
  • Typical VOHV (output VOH undershoot) > 2-V at VCC = 3.3 V, TA = 25°C
  • Ioff supports live insertion, partial-power-down mode, and back-drive protection
  • Latch-up performance exceeds 100 mA per JESD 78, class II
  • ESD protection exceeds JESD 22
    • 2000-V human-body model
    • 200-V machine model
    • 1000-V charged-device model
  • Available in the Texas Instruments NanoFree™ package
  • Supports 5-V VCC operation
  • Inputs accept voltages to 5.5-V
  • Supports down translation to VCC
  • Maximum tpd of 5.9-ns at 3.3-V
  • Low power consumption, 10-µA maximum ICC
  • ±24-mA output drive at 3.3-V
  • Typical VOLP (output ground bounce) < 0.8-V at VCC = 3.3-V, TA = 25°C
  • Typical VOHV (output VOH undershoot) > 2-V at VCC = 3.3 V, TA = 25°C
  • Ioff supports live insertion, partial-power-down mode, and back-drive protection
  • Latch-up performance exceeds 100 mA per JESD 78, class II
  • ESD protection exceeds JESD 22
    • 2000-V human-body model
    • 200-V machine model
    • 1000-V charged-device model

This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

A low level at the preset ( PRE) or clear ( CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

A low level at the preset ( PRE) or clear ( CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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SN74AUP2G02 現行 2 通道、2 輸入、0.8-V 至 3.6-V 低功耗 NOR 閘 Voltage range 0.8V to 3.6V, average propagation delay 8ns, average drive strength 4mA
SN74AUP2G32 現行 2 通道、2 輸入、0.8-V 至 3.6-V 低功耗(< 1uA) OR 閘 Voltage range 0.8V to 3.6V, average propagation delay 8ns, average drive strength 4mA
SN74AUP3G04 現行 3 通道、0.8-V 至 3.6-V 低功耗逆變器 Voltage range 0.8V to 3.6V, average propagation delay 8ns, average drive strength 4mA
SN74AUP2G125 現行 具 3 態輸出的 2 通道、0.8-V 至 3.6-V 低功耗緩衝器 Voltage range 0.8V to 3.6V, average propagation delay 8ns, average drive strength 4mA
SN74AUP2G241 現行 具 3 態輸出的 2 通道、0.8-V 至 3.6-V 低功耗緩衝器 Voltage range 0.8V to 3.6V, average propagation delay 8ns, average drive strength 4mA
SN74AUP3G14 現行 具施密特觸發器輸入的 3 通道 0.8-V 至 3.6-V 低功耗逆變器 Voltage range 0.8V to 3.6V, average propagation delay 8ns, average drive strength 4mA
SN74AUP2G79 現行 低功耗雙路正緣觸發 D 類正反器 Voltage range 0.8V to 3.6V, average propagation delay 8ns, average drive strength 4mA
SN74AUP2G240 現行 具 3 態輸出的 2 通道、0.8-V 至 3.6-V 低功耗緩衝器 Voltage range 0.8V to 3.6V, average propagation delay 8ns, average drive strength 4mA
SN74AUP2G00 現行 2 通道、2 輸入、0.8-V 至 3.6-V 低功耗 NAND 閘 Voltage range 0.8V to 3.6V, average propagation delay 8ns, average drive strength 4mA
SN74AUP2G126 現行 具 3 態輸出的 2 通道、0.8-V 至 3.6-V 低功耗緩衝器 Voltage range 0.8V to 3.6V, average propagation delay 8ns, average drive strength 4mA
SN74AUP2G08 現行 2 通道、2 輸入、0.8V 至 3.6V 低功耗 (< 1uA) AND 閘 Voltage range 0.8V to 3.6V, average propagation delay 8ns, average drive strength 4mA
SN74AUP3G34 現行 3 通道、0.8-V 至 3.6-V 低功耗緩衝器 Voltage range 0.8V to 3.6V, average propagation delay 8ns, average drive strength 4mA
SN74AUP2G80 現行 低功耗雙路正緣觸發 D 類正反器 Voltage range 0.8V to 3.6V, average propagation delay 8ns, average drive strength 4mA
功能相似於所比較的產品。
SN74AHC74 現行 具有清除和預設功能的二路正緣觸發 D 型正反器 Voltage range 2V to 5.5V, average propagation delay 12ns, average drive strength 9mA

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 SN74LVC1G74 Single Positive-Edge-Triggered D-Type Flip-Flop with Clear and Preset datasheet (Rev. G) PDF | HTML 2021/9/14
應用說明 Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022/12/15
Application brief Simplifying Solid-State Relay Designs With Logic PDF | HTML 2021/1/8
白皮書 Solving CMOS Transition Rate Issues Using Schmitt Trigger Solution (Rev. A) 2017/5/1

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