SN74HCS74

現行

具有清除與預設功能的施密特觸發器輸入雙 D 型正緣觸發正反器

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產品規格表

document-pdfAcrobat SN74HCS74 Schmitt-Trigger Input Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset datasheet (Rev. D) (英文) PDF | HTML

SN74HCS74

現行

產品規格表

立即訂購

產品詳細資料

Number of channels

2

Technology family

HCS

Input type

Schmitt-Trigger

Output type

Push-Pull

Clock frequency (max) (MHz)

65

IOL (max) (mA)

7.8

IOH (max) (mA)

-7.8

Supply current (max) (µA)

2

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-40 to 125

Rating

Automotive, Catalog

Number of channels

2

Technology family

HCS

Input type

Schmitt-Trigger

Output type

Push-Pull

Clock frequency (max) (MHz)

65

IOL (max) (mA)

7.8

IOH (max) (mA)

-7.8

Supply current (max) (µA)

2

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-40 to 125

Rating

Automotive, Catalog

SOIC (D)

14

51.9 mm² (8.65 mm × 6 mm)

TSSOP (PW)

14

32 mm² (5 mm × 6.4 mm)

SOT-23-THN (DYY)

14

13.692 mm² (4.2 mm × 3.26 mm)

WQFN (BQA)

14

7.5 mm² (3 mm × 2.5 mm)

Wide operating voltage range: 2 V to 6 V
Schmitt-trigger inputs allow for slow or noisy input signals
Low power consumption
- Typical I_CC of 100 nA
- Typical input leakage current of ±100 nA
±7.8-mA output drive at 6 V
Extended ambient temperature range: –40°C to +125°C, T_A

Wide operating voltage range: 2 V to 6 V
Schmitt-trigger inputs allow for slow or noisy input signals
Low power consumption
- Typical I_CC of 100 nA
- Typical input leakage current of ±100 nA
±7.8-mA output drive at 6 V
Extended ambient temperature range: –40°C to +125°C, T_A

The device contains two independent D-type positive-edge-triggered flip-flops. All inputs include Schmitt triggers, allowing for slow or noisy input signals. A low level at the preset ( PRE) input sets the output high. A low level at the clear ( CLR) input resets the output low. Preset and clear functions are asynchronous and not dependent on the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs (Q, Q) on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the input clock (CLK) signal. Following the hold-time interval, data at the data (D) input can be changed without affecting the levels at the outputs (Q, Q).

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