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電壓轉換器及電平移位器
電壓轉換器

SN74AVC4T774

現行

具有可配置電平移位變化和三態輸出的四位元雙電源匯流排收發器

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產品規格表

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SN74AXC4T774 現行 具有三態輸出和獨立方向控制輸入的 4 位元雙電源匯流排收發器 Pin-to-pin upgrade with a wider voltage range and improved performance

SN74AVC4T774

現行
產品規格表 立即訂購

產品詳細資料

Bits (#) 4 Data rate (max) (Mbps) 380 Topology Push-Pull Direction control (typ) Direction-controlled Vin (min) (V) 1.1 Vin (max) (V) 3.6 Vout (min) (V) 1.1 Vout (max) (V) 3.6 Applications JTAG, SPI, UART Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Prop delay (ns) 4 Technology family AVC Supply current (max) (mA) 0.016 Rating Catalog Operating temperature range (°C) -40 to 125
Bits (#) 4 Data rate (max) (Mbps) 380 Topology Push-Pull Direction control (typ) Direction-controlled Vin (min) (V) 1.1 Vin (max) (V) 3.6 Vout (min) (V) 1.1 Vout (max) (V) 3.6 Applications JTAG, SPI, UART Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Prop delay (ns) 4 Technology family AVC Supply current (max) (mA) 0.016 Rating Catalog Operating temperature range (°C) -40 to 125
SOT-23-THN (DYY) 16 8.4 mm² 4.2 x 2 TSSOP (PW) 16 32 mm² 5 x 6.4 UQFN (RSV) 16 4.68 mm² 2.6 x 1.8 VQFN (RGY) 16 14 mm² 4 x 3.5 WQFN (BQB) 16 8.75 mm² 3.5 x 2.5
  • Each channel has an independent DIR control input
  • Control inputs VIH/VIL levels are referenced to VCCA voltage
  • Fully configurable dual-rail design allows each port to operate over the full 1.1V to 3.6V power-supply range
  • I/Os are 4.6V tolerant
  • Ioff Supports partial power-down-mode operation
  • Typical data rates
    • 380Mbps (1.8V to 3.3V translation)
    • 200Mbps (<1.8V to 3.3V translation)
    • 200Mbps (translate to 2.5V or 1.8V)
    • 150Mbps (translate to 1.5V)
    • 100Mbps (translate to 1.2V)
  • Latch-up performance exceeds 100mA Per JESD 78, class II
  • ESD Protection exceeds the following levels (tested per JESD 22)
    • ±8000V Human-body model (A114-A)
    • 250V Machine model (A115-A)
    • ±1500V Charged-device model (C101)
  • Each channel has an independent DIR control input
  • Control inputs VIH/VIL levels are referenced to VCCA voltage
  • Fully configurable dual-rail design allows each port to operate over the full 1.1V to 3.6V power-supply range
  • I/Os are 4.6V tolerant
  • Ioff Supports partial power-down-mode operation
  • Typical data rates
    • 380Mbps (1.8V to 3.3V translation)
    • 200Mbps (<1.8V to 3.3V translation)
    • 200Mbps (translate to 2.5V or 1.8V)
    • 150Mbps (translate to 1.5V)
    • 100Mbps (translate to 1.2V)
  • Latch-up performance exceeds 100mA Per JESD 78, class II
  • ESD Protection exceeds the following levels (tested per JESD 22)
    • ±8000V Human-body model (A114-A)
    • 250V Machine model (A115-A)
    • ±1500V Charged-device model (C101)

This 4-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.1V to 3.6V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.1 to 3.6V. The SN74AVC4T774 is optimized to operate with VCCA/VCCB set at 1.4V to 3.6V. It is operational with VCCA/VCCB as low as 1.2V. This allows for universal low-voltage bi-directional translation between any of the 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V voltage nodes.

The SN74AVC4T774 is designed for asynchronous communication between data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports in the high-impedance mode. The device transmits data from the A bus to the B bus when the B outputs are activated, and from the B bus to the A bus when the A outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74AVC4T774 is designed so that the control pins (DIR1, DIR2, DIR3, DIR4, and OE) are supplied by VCCA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature ensures that if either VCC input is at GND, then both ports are in the high-impedance state.

For a high-impedance state during power-up or power-down, OE should be tied to VCCA through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Since this device has CMOS inputs, it is very important to not allow them to float. If the inputs are not driven to either a high VCC state, or a low-GND state, an undesirable larger than expected ICC current may result. Since the input voltage settlement is governed by many factors (for example, capacitance, board-layout, package inductance, surrounding conditions, and so forth), ensuring that they these inputs are kept out of erroneous switching states and tying them to either a high or a low level minimizes the leakage-current.

This 4-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.1V to 3.6V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.1 to 3.6V. The SN74AVC4T774 is optimized to operate with VCCA/VCCB set at 1.4V to 3.6V. It is operational with VCCA/VCCB as low as 1.2V. This allows for universal low-voltage bi-directional translation between any of the 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V voltage nodes.

The SN74AVC4T774 is designed for asynchronous communication between data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports in the high-impedance mode. The device transmits data from the A bus to the B bus when the B outputs are activated, and from the B bus to the A bus when the A outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74AVC4T774 is designed so that the control pins (DIR1, DIR2, DIR3, DIR4, and OE) are supplied by VCCA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature ensures that if either VCC input is at GND, then both ports are in the high-impedance state.

For a high-impedance state during power-up or power-down, OE should be tied to VCCA through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Since this device has CMOS inputs, it is very important to not allow them to float. If the inputs are not driven to either a high VCC state, or a low-GND state, an undesirable larger than expected ICC current may result. Since the input voltage settlement is governed by many factors (for example, capacitance, board-layout, package inductance, surrounding conditions, and so forth), ensuring that they these inputs are kept out of erroneous switching states and tying them to either a high or a low level minimizes the leakage-current.
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類型 標題 日期
* Data sheet SN74AVC4T774 4-Bit Dual-Supply Bus Transceiver With Configurable Voltage-Level Shifting and 3-State Outputs With Independent Direction Control Inputs datasheet (Rev. I) PDF | HTML 2025年 2月 10日
Application note Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 2024年 10月 2日
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 2024年 7月 12日
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 2024年 7月 3日
Selection guide Voltage Translation Buying Guide (Rev. A) 2021年 4月 15日
Application note Optimizing Video Doorbell Designs with Common Logic Use Cases (Rev. A) PDF | HTML 2021年 4月 1日
Application note Low Voltage Translation for SPI, UART, RGMII, JTAG Interfaces (Rev. B) PDF | HTML 2021年 3月 29日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
White paper Solving CMOS Transition Rate Issues Using Schmitt Trigger Solution (Rev. A) 2017年 5月 1日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
Application note Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) 2015年 4月 30日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note Selecting the Right Level Translation Solution (Rev. A) 2004年 6月 22日
More literature LCD Module Interface Application Clip 2003年 5月 9日
User guide AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C) 2002年 8月 20日
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002年 6月 13日
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002年 5月 22日
Application note Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B) 1999年 7月 7日
Application note AVC Logic Family Technology and Applications (Rev. A) 1998年 8月 26日
Selection guide Logic Guide (Rev. AC) PDF | HTML 1994年 6月 1日

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AVCLVCDIRCNTRL-EVM — 適用於方向控制雙向轉換裝置、支援 AVC 和 LVC 的通用 EVM

通用 EVM 的設計可支援一、二、四、八通道 LVC 及 AVC 方向控制的轉換裝置。此外也支援相同通道數量的匯流排保留與汽車 -Q1 裝置。AVC 是低電壓轉換裝置，具較低驅動強度 12mA。LVC 是較高的電壓轉換裝置，範圍從 1.65 到 5.5V 且具較高驅動強度 32mA。

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模擬型號

IBIS Model for SN74AVC4T774

SCEM539.ZIP (63 KB) - IBIS Model
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
SOT-23-THN (DYY) 16 Ultra Librarian
TSSOP (PW) 16 Ultra Librarian
UQFN (RSV) 16 Ultra Librarian
VQFN (RGY) 16 Ultra Librarian
WQFN (BQB) 16 Ultra Librarian
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