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電壓轉換器及電平移位器
電壓轉換器

SN74AVC32T245

現行

具有可配置電壓轉換和 3 態輸出的 32 位元雙電源供電匯流排收發器

立即訂購
產品規格表

SN74AVC32T245

現行
產品規格表 立即訂購

產品詳細資料

Bits (#) 32 Data rate (max) (Mbps) 380 Topology Push-Pull Direction control (typ) Direction-controlled Vin (min) (V) 1.2 Vin (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Applications GPIO Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Technology family AVC Supply current (max) (mA) 0.09 Rating Catalog Operating temperature range (°C) -40 to 85
Bits (#) 32 Data rate (max) (Mbps) 380 Topology Push-Pull Direction control (typ) Direction-controlled Vin (min) (V) 1.2 Vin (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Applications GPIO Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Technology family AVC Supply current (max) (mA) 0.09 Rating Catalog Operating temperature range (°C) -40 to 85
NFBGA (NMJ) 96 74.25 mm² 13.5 x 5.5
  • Member of the Texas Instruments Widebus+™ Family
  • Control Inputs VIH/VIL Levels Referenced to VCCA Voltage
  • VCC Isolation Feature – If Either VCC Input is at GND, Both Ports are in the High-Impedance State
  • Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over Full 1.2 V to 3.6 V Power-Supply Range
  • Ioff Supports Partial-Power-Down Mode Operation
  • 4.6 V Tolerant I/Os
  • Max Data Rates
    • 380 Mbps (1.8 V to 3.3 V Level-Shifting)
    • 200 Mbps (< 1.8 V to 3.3 V Level-Shifting)
    • 200 Mbps (Translate to 2.5 V or 1.8 V)
    • 150 Mbps (Translate to 1.5 V)
    • 100 Mbps (Translate to 1.2 V)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 4000 V Human-Body Model (A114-A)
    • 1000 V Charged-Device Model (C101)
  • Member of the Texas Instruments Widebus+™ Family
  • Control Inputs VIH/VIL Levels Referenced to VCCA Voltage
  • VCC Isolation Feature – If Either VCC Input is at GND, Both Ports are in the High-Impedance State
  • Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over Full 1.2 V to 3.6 V Power-Supply Range
  • Ioff Supports Partial-Power-Down Mode Operation
  • 4.6 V Tolerant I/Os
  • Max Data Rates
    • 380 Mbps (1.8 V to 3.3 V Level-Shifting)
    • 200 Mbps (< 1.8 V to 3.3 V Level-Shifting)
    • 200 Mbps (Translate to 2.5 V or 1.8 V)
    • 150 Mbps (Translate to 1.5 V)
    • 100 Mbps (Translate to 1.2 V)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 4000 V Human-Body Model (A114-A)
    • 1000 V Charged-Device Model (C101)

This 32-bit noninverting bus transceiver uses two separate, configurable power-supply rails. The SN74AVC32T245 device is optimized to operate with VCCA/VCCB set from 1.4 V to 3.6 V. It is operational with VCCA/VCCB as low as 1.2 V. The A port is designed to track VCCA. VCCA and accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCB and accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V voltage nodes.

The SN74AVC32T245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable ( OE) input can disable the outputs so the buses are effectively isolated.

The SN74AVC32T245 is designed so that the control pins (1DIR, 2DIR, 3DIR, 4DIR, 1 OE, 2 OE, 3 OE, and 4 OE) are supplied by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature ensures that if either VCC input is at GND, then both ports are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This 32-bit noninverting bus transceiver uses two separate, configurable power-supply rails. The SN74AVC32T245 device is optimized to operate with VCCA/VCCB set from 1.4 V to 3.6 V. It is operational with VCCA/VCCB as low as 1.2 V. The A port is designed to track VCCA. VCCA and accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCB and accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V voltage nodes.

The SN74AVC32T245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable ( OE) input can disable the outputs so the buses are effectively isolated.

The SN74AVC32T245 is designed so that the control pins (1DIR, 2DIR, 3DIR, 4DIR, 1 OE, 2 OE, 3 OE, and 4 OE) are supplied by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature ensures that if either VCC input is at GND, then both ports are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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SN74AVC24T245 現行 具有可配置電壓轉換和 3 態輸出的 24 位元雙電源供電匯流排收發器 Similar function in 24-channel version

技術文件

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重要文件 類型 標題 格式選項 日期
* Data sheet SN74AVC32T245 32-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation, Level-Shifting, and Tri-State Outputs datasheet (Rev. H) PDF | HTML 2020年 11月 11日
Selection guide Logic Guide (Rev. AC) PDF | HTML 2025年 11月 13日
Application note Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 2024年 10月 2日
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 2024年 7月 12日
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 2024年 7月 3日
Selection guide Voltage Translation Buying Guide (Rev. A) 2021年 4月 15日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
Application note Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) 2015年 4月 30日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note Selecting the Right Level Translation Solution (Rev. A) 2004年 6月 22日
More literature LCD Module Interface Application Clip 2003年 5月 9日
User guide AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C) 2002年 8月 20日
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002年 6月 13日
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002年 5月 22日
Application note Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B) 1999年 7月 7日
Application note AVC Logic Family Technology and Applications (Rev. A) 1998年 8月 26日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

模擬型號

SN74AVC32T245 IBIS Model

SCEM462.ZIP (69 KB) - IBIS Model
下載
參考設計

TIDEP0046 — 基於 AM57x 使用 OpenCL 進行 DSP 加速的 Monte-Carlo 模擬參考設計

TI 的高性能 ARM® Cortex®-A15 型 AM57x 處理器也整合了 C66x DSP。這些 DSP 的設計可處理工業、汽車及金融應用領域中經常需要的高訊號和資料處理任務。AM57x OpenCL 實作可讓使用者輕鬆利用 DSP 加速功能執行高運算任務，同時使用標準程式設計模型和語言，因此也就不需要深入了解 DSP 架構。TIDEP0046 TI 參考設計提供使用 DSP 加速功能的範例，以運用標準 C/C++ 程式碼產生超長序列的正常隨機數字。
Design guide: PDF
電路圖: PDF
參考設計

TIDEP0047 — 採用 TI AM57x 處理器參考設計的電源和熱能設計考量

這是以 AM57x 處理器和配套 TPS659037 電源管理積體電路 (PMIC) 為基礎的參考設計。  此設計特別強調針對採用 AM57x 和 TPS659037 設計的系統，在重要電源和散熱設計方面的考量與技術。  其中包括涵蓋電源管理設計、配電網路 (PDN) 設計考量、散熱設計考量、估算功耗及功耗摘要的參考資料與文件。  
Design guide: PDF
電路圖: PDF
參考設計

DLP4500-C350REF — 採用 DLP 技術的高解析度可攜式光導向參考設計

此參考設計採用 DLP® 0.45 吋 WXGA 晶片組，並實作於 DLP® LightCrafter™ 4500 評估模組 (EVM) 中，可為工業、醫療與科學應用提供高解析度、精準圖形的彈性控制。透過免費的 USB 架構 GUI 與 API，開發人員能輕鬆將 TI 創新的數位微鏡裝置 (DMD) 技術與攝影機、感測器、馬達及其他週邊設備整合，打造出高度差異化的 3D 機器視覺系統、3D 印表機與擴增實境顯示器。

 



 

 

Test report: PDF
電路圖: PDF
參考設計

TIDA-00254 — 使用 DLP® 技術且適用於 3D 機器視覺應用的精確點雲產生

3D 機器視覺參考設計採用適用於 LightCrafter™ 系列控制器的德州儀器 DLP® 進階光學控制軟體開發套件 (SDK)，讓開發人員可以透過將 TI 數位微鏡裝置 (DMD) 技術與攝影機、感測器、馬達或其他週邊設備整合，輕鬆構建 3D 點雲。高度差異化的 3D 機器視覺系統採用具備 DLP4500 WXGA 晶片組的 DLP® LightCrafter™ 4500 評估模組 (EVM)，可靈活控制高解析度、精確模式，適用於工業、醫療和保全應用。
Test report: PDF
電路圖: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
NFBGA (NMJ) 96 Ultra Librarian
適用 TI 的評估品項標準條款與條件。

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  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中的可靠性監測
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  • 組裝地點

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