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電壓轉換器

SN74AVC1T45

現行

具有可配置電平移位變化和 3 態輸出的單一位元雙電源供電匯流排收發器

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SN74AXC1T45 現行 單位元雙電源匯流排收發器 Pin-to-pin upgrade with a wider voltage range and improved performance

SN74AVC1T45

現行
立即訂購

產品詳細資料

Bits (#) 1 Data rate (max) (Mbps) 500 Topology Push-Pull Direction control (typ) Fixed-direction Vin (min) (V) 1.2 Vin (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Applications GPIO Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Prop delay (ns) 2.5 Technology family AVC Supply current (max) (mA) 0.02 Rating Catalog Operating temperature range (°C) -40 to 85
Bits (#) 1 Data rate (max) (Mbps) 500 Topology Push-Pull Direction control (typ) Fixed-direction Vin (min) (V) 1.2 Vin (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Applications GPIO Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Prop delay (ns) 2.5 Technology family AVC Supply current (max) (mA) 0.02 Rating Catalog Operating temperature range (°C) -40 to 85
SOT-23 (DBV) 6 8.12 mm² (2.9 mm × 2.8 mm) SOT-5X3 (DRL) 6 2.56 mm² (1.6 mm × 1.6 mm) DSBGA (YZP) 6 2.1875 mm² (— mm × — mm) SOT-SC70 (DCK) 6 4.2 mm² (2 mm × 2.1 mm)
  • Available in the Texas Instruments NanoFree™ package
  • Fully configurable dual-rail design allows each port to operate over the full 1.2V to 3.6V power-supply range
  • VCC isolation feature – if either VCC input is at GND, then both ports are in the high-impedance state
  • DIR input circuit referenced to VCCA
  • ±12mA output drive at 3.3V
  • I/Os are 4.6V tolerant
  • Ioff supports partial-power-down mode operation
  • Typical maximum data rates
    • 500Mbps (1.8V to 3.3V translation)
    • 320Mbps (<1.8V to 3.3V translation)
    • 320Mbps (translate to 2.5V or 1.8V)
    • 280Mbps (translate to 1.5V)
    • 240Mbps (translate to 1.2V)
  • Latch-up performance exceeds 100mA per JESD 78, Class II
  • ESD protection exceeds JESD 22
    • ±2000V Human Body Model (A114-A)
    • 200V Machine Model (A115-A)
    • ±1000V Charged-Device Model (C101)
  • Available in the Texas Instruments NanoFree™ package
  • Fully configurable dual-rail design allows each port to operate over the full 1.2V to 3.6V power-supply range
  • VCC isolation feature – if either VCC input is at GND, then both ports are in the high-impedance state
  • DIR input circuit referenced to VCCA
  • ±12mA output drive at 3.3V
  • I/Os are 4.6V tolerant
  • Ioff supports partial-power-down mode operation
  • Typical maximum data rates
    • 500Mbps (1.8V to 3.3V translation)
    • 320Mbps (<1.8V to 3.3V translation)
    • 320Mbps (translate to 2.5V or 1.8V)
    • 280Mbps (translate to 1.5V)
    • 240Mbps (translate to 1.2V)
  • Latch-up performance exceeds 100mA per JESD 78, Class II
  • ESD protection exceeds JESD 22
    • ±2000V Human Body Model (A114-A)
    • 200V Machine Model (A115-A)
    • ±1000V Charged-Device Model (C101)

This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74AVC1T45 is operational with VCCA/VCCB as low as 1.2V.

The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2V to 3.6V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2V to 3.6V. This allows for universal low-voltage, bidirectional translation between any of the 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V voltage nodes.

The SN74AVC1T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74AVC1T45 is designed so that the DIR input is powered by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature is designed so that if either VCC input is at GND, then both ports are in the high-impedance state.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74AVC1T45 is operational with VCCA/VCCB as low as 1.2V.

The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2V to 3.6V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2V to 3.6V. This allows for universal low-voltage, bidirectional translation between any of the 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V voltage nodes.

The SN74AVC1T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74AVC1T45 is designed so that the DIR input is powered by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature is designed so that if either VCC input is at GND, then both ports are in the high-impedance state.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.
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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 SN74AVC1T45 Single-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation and 3-State Outputs datasheet (Rev. L) PDF | HTML 2026/1/6
應用說明 Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 2024/10/2
應用說明 Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 2024/7/12
應用說明 Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 2024/7/3
選擇指南 Voltage Translation Buying Guide (Rev. A) 2021/4/15
測試報告 TI Power Reference Design for Xilinx® Artix®-7 (AC701) 2014/5/12
使用指南 PMP7977 User's Guide 2013/9/11

設計與開發

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開發板

5-8-LOGIC-EVM — 適用於 5 針腳至 8 針腳 DCK、DCT、DCU、DRL 和 DBV 封裝的通用邏輯評估模組

靈活的 EVM 旨在支援任何針腳數為 5 至 8 支且採用 DCK、DCT、DCU、DRL 或 DBV 封裝的裝置。
使用指南: PDF
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開發板

AVCLVCDIRCNTRL-EVM — 適用於方向控制雙向轉換裝置、支援 AVC 和 LVC 的通用 EVM

通用 EVM 的設計可支援一、二、四、八通道 LVC 及 AVC 方向控制的轉換裝置。此外也支援相同通道數量的匯流排保留與汽車 -Q1 裝置。AVC 是低電壓轉換裝置，具較低驅動強度 12mA。LVC 是較高的電壓轉換裝置，範圍從 1.65 到 5.5V 且具較高驅動強度 32mA。

使用指南: PDF
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開發板

TMP114EVM — 適用於超低高度、1.2-V、高準確度溫度感測器的 TMP114 評估模組

TMP114EVM 讓使用者可評估 TMP114 數位溫度感測器的性能。評估模組 (EVM) 採用 USB 隨身碟型式，配備板載 MSP430F5528 微控制器與使用 I2C 介面的主機和 TMP114 裝置介接。

模組在 EVM 電路板上感測器與主機控制器間設計穿孔。穿孔可在評估過程中提供靈活性：
  • 使用者可將 TMP114 連接至使用者的系統/主機。
  • 使用者可利用 TMP114 裝置將 EVM 主機和軟體連接至使用者的系統。
  • 小型獨立板讓使用者能在系統中放置感測器。
  • 孔間距與常見的 0.1 吋原型模擬板相容。
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開發套件

EVMK2GX — 66AK2Gx 1GHz 評估模組

EVMK2GX（亦稱為「K2G」）1GHz 評估模組 (EVM) 可讓開發人員立即開始評估 66AK2Gx 處理器系列，並加快音訊、工業馬達控制、智慧電網保護和其他高可靠性，即時運算密集應用的開發速度。66AK2Gx 與現有的 KeyStone 式 SoC 裝置類似，可讓 DSP 與 Arm® 核心控制系統中的所有記憶體和週邊設備。此架構有助於實現最大軟體彈性以及以 DSP 或 Arm 為中心的系統設計。

此 EVM 受 Linux 和 TI-RTOS 作業系統的處理器 SDK 支援，並具備 USB、PCIe 與 Gigabit 乙太網路等關鍵週邊設備。它包括電路板管理控制器、SD (...)

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模擬型號

SN74AVC1T45 IBIS Model (Rev. B)

SCEM436B.ZIP (118 KB) - IBIS 模型
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許多 TI 參考設計包含 SN74AVC1T45

使用我們的參考設計選擇工具，以檢視並找出最適合您的應用和參數的設計。
封裝 針腳 CAD 符號、佔位空間與 3D 模型
SOT-23 (DBV) 6 Ultra Librarian
SOT-5X3 (DRL) 6 Ultra Librarian
DSBGA (YZP) 6 Ultra Librarian
SOT-SC70 (DCK) 6 Ultra Librarian
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