SN74AXC1T45

現行

產品詳細資料

Bits (#) 1 Data rate (max) (Mbps) 500 Topology Push-Pull Direction control (typ) Direction-controlled Vin (min) (V) 0.65 Vin (max) (V) 3.6 Vout (min) (V) 0.65 Vout (max) (V) 3.6 Applications GPIO Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff), Vcc isolation Prop delay (ns) 5 Technology family AXC Supply current (max) (mA) 0.016 Rating Catalog Operating temperature range (°C) -40 to 125
Bits (#) 1 Data rate (max) (Mbps) 500 Topology Push-Pull Direction control (typ) Direction-controlled Vin (min) (V) 0.65 Vin (max) (V) 3.6 Vout (min) (V) 0.65 Vout (max) (V) 3.6 Applications GPIO Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff), Vcc isolation Prop delay (ns) 5 Technology family AXC Supply current (max) (mA) 0.016 Rating Catalog Operating temperature range (°C) -40 to 125
SOT-SC70 (DCK) 6 4.2 mm² (2 mm × 2.1 mm) SOT-23 (DBV) 6 8.12 mm² (2.9 mm × 2.8 mm) X2SON (DTQ) 6 0.8 mm² (1 mm × 0.8 mm) X2SON (DEA) 6 1 mm² (1 mm × 1 mm) SOT-5X3 (DRL) 6 2.56 mm² (1.6 mm × 1.6 mm)
  • Up and down translation across 0.65 V to 3.6 V
  • Operating temperature: –40°C to +125°C
  • Designed with glitch suppression circuitry to improve power sequencing performance
  • Maximum quiescent current (ICCA + ICCB) of 10µA (85°C maximum) and 16µA (125°C maximum)
  • Up to 500Mbps support when translating from 1.8 to 3.3V
  • VCC isolation feature:
    • If either VCC input is below 100mV, all I/Os outputs are disabled and become high-impedance
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100mA per JESD 78, Class II
  • ESD protection exceeds JESD 22:
    • 8000-V human body model
    • 1000-V charged-device model
  • Up and down translation across 0.65 V to 3.6 V
  • Operating temperature: –40°C to +125°C
  • Designed with glitch suppression circuitry to improve power sequencing performance
  • Maximum quiescent current (ICCA + ICCB) of 10µA (85°C maximum) and 16µA (125°C maximum)
  • Up to 500Mbps support when translating from 1.8 to 3.3V
  • VCC isolation feature:
    • If either VCC input is below 100mV, all I/Os outputs are disabled and become high-impedance
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100mA per JESD 78, Class II
  • ESD protection exceeds JESD 22:
    • 8000-V human body model
    • 1000-V charged-device model

The SN74AXC1T45 is a single-bit noninverting bus transceiver that uses two separate configurable power-supply rails. The device is operational with both VCCA and VCCB supplies as low as 0.65 V. The A port is designed to track VCCA, which accepts any supply voltage from 0.65 V to 3.6V. The B port is designed to track VCCB, which also accepts any supply voltage from 0.65 V to 3.6V.

The DIR pin determines the direction of signal propagation. With the DIR pin configured HIGH, translation is from Port A to Port B. With DIR configured LOW, translation is from Port B to Port A. The DIR pin is referenced to VCCA, meaning that its logic-high and logic-low thresholds track with VCCA.

This device is fully specified for partial-power-down applications using the Ioff current. The Ioff protection circuitry ensures that no excessive current is drawn from or to an input, output, or combined I/O that is biased to a specific voltage while the device is powered down.

The VCC isolation feature ensures that if either VCCA or VCCB is less than 100mV, both I/O ports enter a high-impedance state by disabling their outputs.

The glitch suppression circuitry enables either supply rail to be powered on or off in any order, providing robust power sequencing performance.

The SN74AXC1T45 is a single-bit noninverting bus transceiver that uses two separate configurable power-supply rails. The device is operational with both VCCA and VCCB supplies as low as 0.65 V. The A port is designed to track VCCA, which accepts any supply voltage from 0.65 V to 3.6V. The B port is designed to track VCCB, which also accepts any supply voltage from 0.65 V to 3.6V.

The DIR pin determines the direction of signal propagation. With the DIR pin configured HIGH, translation is from Port A to Port B. With DIR configured LOW, translation is from Port B to Port A. The DIR pin is referenced to VCCA, meaning that its logic-high and logic-low thresholds track with VCCA.

This device is fully specified for partial-power-down applications using the Ioff current. The Ioff protection circuitry ensures that no excessive current is drawn from or to an input, output, or combined I/O that is biased to a specific voltage while the device is powered down.

The VCC isolation feature ensures that if either VCCA or VCCB is less than 100mV, both I/O ports enter a high-impedance state by disabling their outputs.

The glitch suppression circuitry enables either supply rail to be powered on or off in any order, providing robust power sequencing performance.

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模擬型號

SN74AXC1T45 IBIS Model (Rev. A)

SCEM581A.ZIP (51 KB) - IBIS 模型
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SOT-SC70 (DCK) 6 Ultra Librarian
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