SN74AUP2G07

現行

具開汲極輸出的 2 通道、0.8-V 至 3.6-V 低功耗緩衝器

立即訂購

產品規格表

document-pdfAcrobat SN74AUP2G07 Low-Power Dual Buffer/Driver With Open-Drain Outputs datasheet (Rev. E) (英文) PDF | HTML

SN74AUP2G07

現行

產品規格表

立即訂購

產品詳細資料

Technology family

AUP

Number of channels

2

IOL (max) (mA)

4

Supply current (max) (µA)

0.9

IOH (max) (mA)

0

Input type

Standard CMOS

Output type

Open-drain

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Technology family

AUP

Number of channels

2

IOL (max) (mA)

4

Supply current (max) (µA)

0.9

IOH (max) (mA)

0

Input type

Standard CMOS

Output type

Open-drain

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

X2SON (DSF)

6

1 mm² (1 mm × 1 mm)

SOT-SC70 (DCK)

6

4.2 mm² (2 mm × 2.1 mm)

DSBGA (YFP)

6

1.4000000000000001 mm² (— mm × — mm)

USON (DRY)

6

1.45 mm² (1.45 mm × 1 mm)

Low static-power consumption (I_CC = 0.9 µA maximum)
Low dynamic-power consumption (C_pd = 1 pF typical at 3.3 V)
Low input capacitance (C_i = 1.5 pF typical)
Low noise – overshoot and undershoot <10% of V_CC
I_off supports live insertion, partial-power-down mode, and back-drive protection
Input hysteresis allows slow input transition and better switching noise immunity at the input (V_hys = 250 mV typical at 3.3 V)
Wide operating V_CC range of 0.8 V to 3.6 V
Optimized for 3.3 V operation
3.6-V I/O tolerant to support mixed-mode signal operation
t_pd = 3.3 ns maximum at 3.3 V
Suitable for point-to-point applications
Latch-up performance exceeds 100 mA per JESD 78, Class II
ESD performance tested per JESD 22
- 4500-V human-body model
- 1500-V charged-device model

Low static-power consumption (I_CC = 0.9 µA maximum)
Low dynamic-power consumption (C_pd = 1 pF typical at 3.3 V)
Low input capacitance (C_i = 1.5 pF typical)
Low noise – overshoot and undershoot <10% of V_CC
I_off supports live insertion, partial-power-down mode, and back-drive protection
Input hysteresis allows slow input transition and better switching noise immunity at the input (V_hys = 250 mV typical at 3.3 V)
Wide operating V_CC range of 0.8 V to 3.6 V
Optimized for 3.3 V operation
3.6-V I/O tolerant to support mixed-mode signal operation
t_pd = 3.3 ns maximum at 3.3 V
Suitable for point-to-point applications
Latch-up performance exceeds 100 mA per JESD 78, Class II
ESD performance tested per JESD 22
- 4500-V human-body model
- 1500-V charged-device model

The SN74AUP2G07 device is a dual buffer gate with open drain output that operates from 0.8 V to 3.6 V.

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SN74LVC2G07

現行

具有開漏輸出的 2 通道、1.65-V 至 5.5-V 緩衝器 Voltage range 1.65V to 5.5V, average propagation delay 5.5ns, average drive strength 24mA

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重要文件	類型	標題	格式選項	下載最新的英文版本		日期
*	資料表	SN74AUP2G07 Low-Power Dual Buffer/Driver With Open-Drain Outputs datasheet (Rev. E)	PDF \| HTML			2021/10/4
	Application brief	Understanding Schmitt Triggers (Rev. B)	PDF \| HTML			2025/4/17