產品詳細資料

Technology family AUP Number of channels 1 Inputs per channel 1 IOL (max) (mA) 4 IOH (max) (mA) -4 Input type Schmitt-Trigger Output type 3-State Features Output enable, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 85
Technology family AUP Number of channels 1 Inputs per channel 1 IOL (max) (mA) 4 IOH (max) (mA) -4 Input type Schmitt-Trigger Output type 3-State Features Output enable, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 85
VSSOP (DCU) 8 6.2 mm² (2 mm × 3.1 mm) SSOP (DCT) 8 11.8 mm² (2.95 mm × 4 mm) DSBGA (YZP) 8 2.8125 mm² (— mm × — mm)
  • Available in the Texas Instruments
    NanoFree™ Package
  • Low Static-Power Consumption
    (ICC = 0.9 µA Max)
  • Low Dynamic-Power Consumption
    (Cpd = 5 pF Typ at 3.3 V)
  • Low Input Capacitance (CI = 1.5 pF)
  • Low Noise – Overshoot and Undershoot
    <10% of VCC
  • Input-Disable Feature Allows Floating Input Conditions
  • Ioff Supports Partial-Power-Down Mode Operation
  • Includes Schmitt-Trigger Inputs
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 7.4 ns Max at 3.3 V
  • Suitable for Point-to-Point Applications
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

NanoFree Is a trademark of Texas Instruments.

  • Available in the Texas Instruments
    NanoFree™ Package
  • Low Static-Power Consumption
    (ICC = 0.9 µA Max)
  • Low Dynamic-Power Consumption
    (Cpd = 5 pF Typ at 3.3 V)
  • Low Input Capacitance (CI = 1.5 pF)
  • Low Noise – Overshoot and Undershoot
    <10% of VCC
  • Input-Disable Feature Allows Floating Input Conditions
  • Ioff Supports Partial-Power-Down Mode Operation
  • Includes Schmitt-Trigger Inputs
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 7.4 ns Max at 3.3 V
  • Suitable for Point-to-Point Applications
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

NanoFree Is a trademark of Texas Instruments.

The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see Figures 1 and 2).

The SN74AUP1G99 features configurable multiple functions with a 3-state output. This device has the input-disable feature, which allows floating input signals. The inputs and output are disabled when the output-enable (OE) input is high. When OE is low, the output state is determined by 16 patterns of 4-bit input. The user can choose the logic functions, such as MUX, AND, OR, NAND, NOR, XOR, XNOR, inverter, and buffer. All inputs can be connected to VCC or GND.

This device functions as an independent gate with Schmitt-trigger inputs, which allows for slow input transition and better switching noise immunity at the input.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see Figures 1 and 2).

The SN74AUP1G99 features configurable multiple functions with a 3-state output. This device has the input-disable feature, which allows floating input signals. The inputs and output are disabled when the output-enable (OE) input is high. When OE is low, the output state is determined by 16 patterns of 4-bit input. The user can choose the logic functions, such as MUX, AND, OR, NAND, NOR, XOR, XNOR, inverter, and buffer. All inputs can be connected to VCC or GND.

This device functions as an independent gate with Schmitt-trigger inputs, which allows for slow input transition and better switching noise immunity at the input.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

下載 觀看有字幕稿的影片 影片

您可能會感興趣的類似產品

open-in-new 比較替代產品
針腳對針腳的功能與所比較的裝置相同。
SN74AUC2G02 現行 2 通道、2 輸入、0.8-V 至 2.7-V 高速 NOR 閘 Voltage range 0.8V to 2.7V, average propagation delay 1.7ns, average drive strength 9mA
SN74AUC1G74 現行 具有清除和預設功能的單路正緣觸發 D 型正反器 Voltage range 0.8V to 2.7V, average propagation delay 1.7ns, average drive strength 9mA
SN74AUC2G86 現行 2 通道、2 輸入、0.8-V 至 2.7-V 高速 XOR (exclusive OR) 閘 Voltage range 0.8V to 2.7V, average propagation delay 1.7ns, average drive strength 9mA
SN74AUC2G08 現行 2 通道、2 輸入、0.8V 至 2.7V 超高速 (2.4 ns) AND 閘 Voltage range 0.8V to 2.7V, average propagation delay 1.7ns, average drive strength 9mA
SN74AUC2G00 現行 2 通道、2 輸入、0.8-V 至 2.7-V 高速 NAND 閘 Voltage range 0.8V to 2.7V, average propagation delay 1.7ns, average drive strength 9mA
SN74AUC2G125 現行 具有 3 態輸出的 2 通道、0.8-V 至 2.7-V 高速緩衝器 Voltage range 0.8V to 2.7V, average propagation delay 1.7ns, average drive strength 9mA
SN74AUC2G126 現行 具有 3 態輸出的 2 通道、0.8-V 至 2.7-V 高速緩衝器 Voltage range 0.8V to 2.7V, average propagation delay 1.7ns, average drive strength 9mA
SN74LVC1G99 現行 具有 3 態輸出的超級可配置多功能閘 Voltage range 1.65V to 5.5V, average propagation delay 5.5ns, average drive strength 24mA
SN74AUC2G32 現行 2 通道、2 輸入、0.8V 至 2.7V 超高速 (2.4 ns) OR 閘 Voltage range 0.8V to 2.7V, average propagation delay 1.7ns, average drive strength 9mA
SN74AUC2G240 現行 具有 3 態輸出的 2 通道、0.8-V 至 2.7-V 高速逆變器 Voltage range 0.8V to 2.7V, average propagation delay 1.7ns, average drive strength 9mA

技術文件

找不到結果。請清除您的搜尋條件,然後再試一次。
檢視所有 3
重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 Low-Power Ultra-Configurable Multiple-Function Gate With 3-State Outputs datasheet (Rev. C) 2007/7/9
Application brief Understanding Schmitt Triggers (Rev. B) PDF | HTML 2025/4/17
Application brief Utilizing Configurable Logic in System Design PDF | HTML 2024/10/30

設計與開發

如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

5-8-LOGIC-EVM — 適用於 5 針腳至 8 針腳 DCK、DCT、DCU、DRL 和 DBV 封裝的通用邏輯評估模組

靈活的 EVM 旨在支援任何針腳數為 5 至 8 支且採用 DCK、DCT、DCU、DRL 或 DBV 封裝的裝置。
使用指南: PDF
支援產品和硬體
有庫存
限制:
??asset.out-of-stock-ti_zh_TW??
無法提供
模擬型號

SN74AUP1G99 IBIS Model (Rev. A)

SCEM458 (458 KB) - IBIS 模型
支援產品和硬體
封裝 針腳 CAD 符號、佔位空間與 3D 模型
VSSOP (DCU) 8 Ultra Librarian
SSOP (DCT) 8 Ultra Librarian
DSBGA (YZP) 8 Ultra Librarian

訂購與品質

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

內容係由 TI 和社群貢獻者依「現狀」提供,且不構成 TI 規範。檢視使用條款

若有關於品質、封裝或訂購 TI 產品的問題,請參閱 TI 支援。​​​​​​​​​​​​​​

影片