SN54SC8T541-SEP
- Vendor item drawing available, VID V62/25632-01XE
- Radiation - Total Ionizing Dose
(TID):
- TID characterized up to 50krad(Si)
- TID performance assurance up to 30krad(Si)
- Radiation Lot Acceptance Testing (RLAT) for every wafer lot up to 30krad(Si)
- Radiation - Single-Event Effects (SEE):
- Single Event Latch-Up (SEL) immune up to 50MeV-cm2/mg at 125°C
- Single Event Transient (SET) characterized up to LET = 50MeV-cm2/mg
-
Wide operating range of 1.2V to 5.5V
-
Single-supply voltage translator:
-
Up translation:
-
1.2V to 1.8V
-
1.5V to 2.5V
-
1.8V to 3.3V
-
3.3V to 5.0V
-
-
Down translation:
- 5.0V, 3.3V, 2.5V to 1.8V
- 5.0V, 3.3V to 2.5V
- 5.0V to 3.3V
-
- 5.5V tolerant input pins
- Supports standard pinouts
- Up to 150Mbps with 5V or 3.3V VCC
- Latch-up performance exceeds 250mA per JESD 17
- Space enhanced plastic:
- Supports defense and aerospace applications
- Controlled baseline
- Au bondwire and NiPdAu lead finish
- Meets NASA ASTM E595 outgassing specification
- One fabrication, assembly, and test site
- Extended product life cycle
- Product traceability
The SN54SC8T541-SEP contains eight buffers with 3-state outputs. The active low output enable pins (OE1 and OE2) control all eight channels, and are configured so that both must be low for the outputs to be active. When the outputs are enabled, the outputs are actively driven low or high. When the outputs are disabled, the outputs are set into the high-impedance state. The output level is referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.
The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2V input to 1.8V output or 1.8V input to 3.3V output). In addition, the 5V tolerant input pins enable down translation (for example, 3.3V to 2.5V output).
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | SN54SC8T541-SEP Radiation Tolerant, Octal Buffers and Line Drivers With 3-State Outputs and Logic Level Shifter datasheet (Rev. A) | PDF | HTML | 2025/1/28 | ||
| * | 輻射及可靠性報告 | SN54SC8T541-SEP Total Ionizing Dose (TID) Report | 2025/2/19 | |||
| * | 輻射及可靠性報告 | SN54SC8T541-SEP Production Flow and Reliability Report | PDF | HTML | 2025/1/21 | ||
| * | 輻射及可靠性報告 | SN54SC8T541-SEP Single Event Effects Report | PDF | HTML | 2025/1/16 | ||
| 選擇指南 | TI Space Products (Rev. L) | 2026/3/27 | ||||
| 應用說明 | Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators | PDF | HTML | 2024/10/2 |
設計與開發
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14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| TSSOP (PW) | 20 | Ultra Librarian |