SN54SC6T06-SEP
- Vendor item drawing available, VID V62/24616
- Total ionizing dose characterized at 30 krad (Si)
- Total ionizing dose radiation lot acceptance testing (TID RLAT) for every wafer lot to 30 krad (Si)
- Single-event effects (SEE) characterized:
- Single event latch-up (SEL) immune to linear energy transfer (LET) = 43 MeV-cm2 /mg
- Single event transient (SET) characterized to 43 MeV-cm2 /mg
- Wide operating range of 1.2V to 5.5V
- Single-supply translating gates at 5/3.3/2.5/1.8/1.2V VCC
- TTL compatible inputs:
- Up translation:
- 1.8V – Inputs from 1.2V
- 2.5V – Inputs from 1.8V
- 3.3V – Inputs from 1.8V, 2.5V
- 5.0V – Inputs from 2.5V, 3.3V
- Down translation:
-
1.2V – Inputs from 1.8V, 2.5V, 3.3V, 5.0V
- 1.8V – Inputs from 2.5V, 3.3V, 5.0V
- 2.5V – Inputs from 3.3V, 5.0V
- 3.3V – Inputs from 5.0V
-
- Up translation:
- TTL compatible inputs:
- 5.5V tolerant input pins
- Output drive up to 25mA AT 5V
- Latch-up performance exceeds 250mA per JESD 17
- Space enhanced plastic (SEP)
- Controlled baseline
- Gold bondwire
- NiPdAu lead finish
- One assembly and test site
- One fabrication site
- Military (–55°C to 125°C) temperature range
- Extended product life cycle
- Product traceability
- Meets NASAs ASTM E595 outgassing specification
The SN54SC6T06-SEP device contains six independent inverters with open-drain outputs and extended voltage operation to allow for level translation. Each inverter performs the Boolean function Y = A in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.2V, 1.8V, 2.5V, 3.3V, and 5V CMOS levels.
The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example 1.2V input to 1.8V output or 1.8V input to 3.3V output). Additionally, the 5V tolerant input pins enable down translation (for example 3.3V to 2.5V output).
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | SN54SC6T06-SEP Radiation Tolerant, Hex Inverter Buffers/Drivers With Open-Drain Outputs datasheet | PDF | HTML | 2024/1/19 | ||
| * | 輻射及可靠性報告 | SN54SC6T06-SEP Production Flow and Reliability Report | PDF | HTML | 2024/4/10 | ||
| * | 輻射及可靠性報告 | SN54SC6T07-SEP Single Event Effects Radiation Report | PDF | HTML | 2024/2/21 | ||
| * | 輻射及可靠性報告 | SN54SC6T06-SEP Total Ionizing Dose (TID) Report | PDF | HTML | 2024/2/8 | ||
| 應用說明 | Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators | PDF | HTML | 2024/10/2 | |||
| Application brief | TI Space Enhanced Plastic Logic Overview and Applications in Low-Earth Orbit Satellite Platforms | PDF | HTML | 2024/9/10 | |||
| 應用說明 | Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators | PDF | HTML | 2024/7/12 | |||
| 應用說明 | Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) | PDF | HTML | 2024/7/3 |
設計與開發
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14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| TSSOP (PW) | 14 | Ultra Librarian |