SN54SC1G175-SEP
- VID V62/26610
- Radiation - Total Ionizing Dose
(TID):
- TID characterized up to 50krad(Si)
- TID performance assurance up to 30krad(Si)
- Radiation Lot Acceptance Testing (RLAT) for every wafer lot up to 30krad(Si)
- Radiation - Single-Event Effects (SEE):
- Single Event Latch-Up (SEL) immune up to 50MeV-cm2/mg at 125°C
- Single Event Transient (SET) characterized up to LET = 50MeV-cm2/mg
-
Wide operating range of 1.2V to 5.5V
- 5.5V tolerant input pins
- Supports standard pinouts
- Up to 150Mbps with 5V or 3.3V VCC
- Latch-up performance exceeds 100mA per JESD 78
- Space enhanced plastic:
- Supports Defense and Aerospace Applications
- Controlled baseline
- Au bondwire and NiPdAu lead finish
- Meets NASA ASTM E595 outgassing specification
- One fabrication, assembly, and test site
- Extended product life cycle
- Product traceability
The SN54SC1G175-SEP device is a single D-type flip-flop with asynchronous clear (CLR) input. When CLR is HIGH, data from the input pin (D) transfers to the output pin (Q) on the clock’s (CLK) rising edge. When CLR is LOW, the Q is forced into the LOW state, regardless of the clock edge or data on D.
技術文件
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| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | SN54SC1G175-SEP Single D-Type Flip-Flop With Asynchronous Clear datasheet | PDF | HTML | 2026/2/20 | ||
| * | 輻射及可靠性報告 | SN54SC1G175-SEP Total Ionizing Dose (TID) Report | 2026/2/6 | |||
| * | 輻射及可靠性報告 | SN54SC1G175-SEP Single-Event Effects (SEE) Radiation Report | PDF | HTML | 2026/2/6 | ||
| * | 輻射及可靠性報告 | SN54SC1G175-SEP Production Flow and Reliability Report | PDF | HTML | 2026/2/6 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
開發板
5-8-LOGIC-EVM — 適用於 5 針腳至 8 針腳 DCK、DCT、DCU、DRL 和 DBV 封裝的通用邏輯評估模組
靈活的 EVM 旨在支援任何針腳數為 5 至 8 支且採用 DCK、DCT、DCU、DRL 或 DBV 封裝的裝置。
使用指南:
PDF
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOT-23 (DBV) | 6 | Ultra Librarian |