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可編程與可變增益放大器 (PGA 與 VGA)

PGA117

現行

具 10 通道多工器的零漂移、100-µV 偏移、12-nV/√Hz 雜訊、RRO (範圍增益) 可編程增益放大器

立即訂購
產品規格表

PGA117

現行
產品規格表 立即訂購

產品詳細資料

PGA/VGA PGA Number of channels 10 Vs (min) (V) 2.2 Vs (max) (V) 5.5 Input type Single-ended Output type Single-ended Input offset drift (±) (typ) (µV/°C) 0.6 Interface type SPI Noise at 1 kHz (typ) (V√Hz) 0.000000013 BW at Acl (MHz) 10 Acl, min spec gain (V/V) 1 Gain (max) (dB) 46 Architecture CMOS Features Daisy chain, Scope gains, Shutdown Vos (offset voltage at 25°C) (typ) (mV) 0.025 Input voltage noise (typ) (µV√Hz) 0.012 Slew rate (typ) (V/µs) 3 Iq per channel (typ) (mA) 1.08 Gain error (typ) (%) 0.006 Gain drift (max) (ppm/°C) 0.5 Rating Catalog Operating temperature range (°C) -40 to 125
PGA/VGA PGA Number of channels 10 Vs (min) (V) 2.2 Vs (max) (V) 5.5 Input type Single-ended Output type Single-ended Input offset drift (±) (typ) (µV/°C) 0.6 Interface type SPI Noise at 1 kHz (typ) (V√Hz) 0.000000013 BW at Acl (MHz) 10 Acl, min spec gain (V/V) 1 Gain (max) (dB) 46 Architecture CMOS Features Daisy chain, Scope gains, Shutdown Vos (offset voltage at 25°C) (typ) (mV) 0.025 Input voltage noise (typ) (µV√Hz) 0.012 Slew rate (typ) (V/µs) 3 Iq per channel (typ) (mA) 1.08 Gain error (typ) (%) 0.006 Gain drift (max) (ppm/°C) 0.5 Rating Catalog Operating temperature range (°C) -40 to 125
TSSOP (PW) 20 41.6 mm² (6.5 mm × 6.4 mm)
  • Rail-to-Rail Input and Output
  • Offset: 25 µV (Typical), 100 µV
    (Maximum)
  • Zerø Drift: 0.35 µV/°C (Typical), 1.2 µV/°C
    (Maximum)
  • Low Noise: 12 nV/√Hz
  • Input Offset Current: ±5 nA Maximum (25°C)
  • Gain Error: 0.1% Maximum (G ≥ 32),
    0.3% Maximum (G > 32)
  • Binary Gains: 1, 2, 4, 8, 16, 32, 64, 128 (PGA112,
    PGA116)
  • Scope Gains: 1, 2, 5, 10, 20, 50, 100, 200
    (PGA113, PGA117)
  • Gain Switching Time: 200 ns
  • 2 Channel MUX: PGA112, PGA113
    10 Channel MUX: PGA116, PGA117
  • Four Internal Calibration Channels
  • Amplifier Optimized for Driving CDAC ADCs
  • Output Swing: 50 mV to Supply Rails
  • AVDD and DVDD for Mixed Voltage Systems
  • IQ = 1.1 mA (Typical)
  • Software and Hardware Shutdown: IQ ≤ 4 µA
    (Typical)
  • Temperature Range: –40°C to 125°C
  • SPI™ Interface (10 MHz) With Daisy-Chain
    Capability
  • Rail-to-Rail Input and Output
  • Offset: 25 µV (Typical), 100 µV
    (Maximum)
  • Zerø Drift: 0.35 µV/°C (Typical), 1.2 µV/°C
    (Maximum)
  • Low Noise: 12 nV/√Hz
  • Input Offset Current: ±5 nA Maximum (25°C)
  • Gain Error: 0.1% Maximum (G ≥ 32),
    0.3% Maximum (G > 32)
  • Binary Gains: 1, 2, 4, 8, 16, 32, 64, 128 (PGA112,
    PGA116)
  • Scope Gains: 1, 2, 5, 10, 20, 50, 100, 200
    (PGA113, PGA117)
  • Gain Switching Time: 200 ns
  • 2 Channel MUX: PGA112, PGA113
    10 Channel MUX: PGA116, PGA117
  • Four Internal Calibration Channels
  • Amplifier Optimized for Driving CDAC ADCs
  • Output Swing: 50 mV to Supply Rails
  • AVDD and DVDD for Mixed Voltage Systems
  • IQ = 1.1 mA (Typical)
  • Software and Hardware Shutdown: IQ ≤ 4 µA
    (Typical)
  • Temperature Range: –40°C to 125°C
  • SPI™ Interface (10 MHz) With Daisy-Chain
    Capability

The PGA112 and PGA113 devices (binary and scope gains) offer two analog inputs, a three-pin SPI interface, and software shutdown in a 10-pin, VSSOP package. The PGA116 and PGA117 (binary and scope gains) offer 10 analog inputs, a SPI interface with daisy-chain capability, and hardware and software shutdown in a 20-pin TSSOP package.

All versions provide internal calibration channels for system-level calibration. The channels are tied to GND, 0.9 VCAL, 0.1 VCAL, and VREF, respectively. VCAL, an external voltage connected to Channel 0, is used as the system calibration reference. Binary gains are: 1, 2, 4, 8, 16, 32, 64, and 128; scope gains are: 1, 2, 5, 10, 20, 50, 100, and 200.

The PGA112 and PGA113 devices (binary and scope gains) offer two analog inputs, a three-pin SPI interface, and software shutdown in a 10-pin, VSSOP package. The PGA116 and PGA117 (binary and scope gains) offer 10 analog inputs, a SPI interface with daisy-chain capability, and hardware and software shutdown in a 20-pin TSSOP package.

All versions provide internal calibration channels for system-level calibration. The channels are tied to GND, 0.9 VCAL, 0.1 VCAL, and VREF, respectively. VCAL, an external voltage connected to Channel 0, is used as the system calibration reference. Binary gains are: 1, 2, 4, 8, 16, 32, 64, and 128; scope gains are: 1, 2, 5, 10, 20, 50, 100, and 200.
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針腳對針腳的功能與所比較的裝置相同。
PGA116 現行 具 10 通道多工器的零漂移、100-µV 偏移、12-nV/√Hz 雜訊、RRO (二進位增益) 可編程增益放大器 This device offers binary gains 1, 2, 4, 8, 16, 32, 64, 128 instead of scope gains
功能相同，但針腳輸出與所比較的裝置不同。
PGA113 現行 具 2 通道多工器的零漂移、100-µV 偏移、12-nV/√Hz 雜訊、RRO (範圍增益) 可編程增益放大器 This device offers 2 channel mux instead of 10 channel mux,
PGA112 現行 具 2 通道多工器的零漂移、100-µV 偏移、12-nV/√Hz 雜訊、RRO (二進位增益) 可編程增益放大器 This device offers 2 channel mux instead of 10 channel mux, and binary gains instead of scope gains.

技術文件

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 PGA11x Zerø-Drift Programmable Gain Amplifier With Mux datasheet (Rev. C) PDF | HTML 2015/11/30

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參考設計

TIDA-00130 — 適用斷路器 (ACB/MCCB-ETU) 的零飄移 PGA 架構類比前端設計

此參考設計適用於模製外殼斷路器 (MCCB) 電子跳脫裝置。  程式化增益放大器的設計，可做為過電流接地故障繼電器的電流監控。此設計運用零漂移程式化放大器，提供 ±10% 拾取 (A) 準確度 和 0% 至 -20% 的延遲時間 (秒) 準確度。此外，本解決方案的設計用途為因應嚴苛的環境條件，其加入 -10 至 70 μm 的周圍不敏感度範圍，以及高電磁抗擾度等功能。最後，此設計的類比前端會與 TI MSP430 MCU 無縫介接，以加快評估速度及上市時間。

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