DS280DF810
- Octal-channel multi-rate retimer with integrated signal conditioning
- All channels lock independently from 20.2Gbps to 28.4Gbps (including sub-rates like 10.1376Gbps, 10.3125Gbps, 12.5Gbps, and more)
- Ultra-low latency: <500 ps typical for 28.4Gbps data rate
- Single power supply, No Low-Jitter Reference Clock Required, and Integrated AC coupling capacitors to reduce board routing complexity and BOM cost
- Integrated 2×2 cross point
- Adaptive continuous time linear equalizer (CTLE)
- Adaptive decision feedback equalizer (DFE)
- Low-jitter transmitter with 3-Tap FIR Filter
- Combined equalization supporting 35+dB channel loss at 12.9GHz; 30+dB channel loss at 14GHz
- Adjustable transmit amplitude: 205mVppd to 1225mVppd (typical)
- On-chip eye opening monitor (EOM), PRBS pattern checker/generator
- Small 8.00mm × 13.00mm BGA package with easy flow-through routing
- Unique pinout allows routing high-speed signals underneath the package
- Pin-compatible repeater available
- Extended temperature range: −40 °C to 85 °C
The DS280DF810 is an eight-channel multi-rate Retimer with integrated signal conditioning. It is used to extend the reach and robustness of long, lossy, crosstalk-impaired high-speed serial links while achieving a bit error rate (BER) of 10-15 or less.
Each channel of the DS280DF810 independently locks to serial data rates in a continuous range from 20.2Gbps to 28.4Gbps or to any supported sub-rate (÷2 and ÷4), including key data rates such as 10.1376Gbps, 10.3125Gbps, and 12.5Gbps, which allows the DS280DF810 to support individual lane Forward Error Correction (FEC) pass-through.
Integrated physical AC coupling capacitors (TX and RX) eliminate the need for external capacitors on the PCB. The DS280DF810 has a single power supply and minimal need for external components. These features reduce PCB routing complexity and BOM cost.
The advanced equalization features of the DS280DF810 include a low-jitter 3-tap transmit finite impulse response (FIR) filter, an adaptive continuous-time linear equalizer (CTLE), and an adaptive decision feedback equalizer (DFE). This enables reach extension for lossy interconnect and backplanes with multiple connectors and crosstalk. The integrated CDR function is an excellent choice for front-port optical module applications to reset the jitter budget and retimer the high-speed serial data. The DS280DF810 implements 2x2 cross-point on each channel pair, providing the host with both lane crossing and fanout options.
The DS280DF810 can be configured either via the SMBus or through an external EEPROM. Up to 16 devices can share a single EEPROM. A non-disruptive on-chip eye monitor and a PRBS generator and checker allow for in-system diagnostics.
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技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | DS280DF810 28Gbps Multi-Rate 8-Channel Retimer datasheet (Rev. B) | PDF | HTML | 2024/2/1 | ||
| 應用說明 | Implementing Pin Compatible Ethernet Redrivers and Retimers | PDF | HTML | 2024/10/28 | |||
| 應用說明 | Optimal Implementation of 25G-28G Ethernet Retimers versus Redrivers (Rev. B) | PDF | HTML | 2023/5/1 | |||
| 應用說明 | Ethernet, Clock and Data Recovery, and Temperature Optimization | PDF | HTML | 2022/7/29 | |||
| 應用說明 | DS2X0DF810 Junction Temperature Readback and Temperature Lock Range (TLR) Extens | PDF | HTML | 2021/5/24 | |||
| 更多文件說明 | Advanced Signal Conditioning Made Easy and Efficient | 2017/1/12 | ||||
| 類比設計期刊 | Green box testing: A method for optimizing high-speed serial links | 2016/7/21 | ||||
| 應用說明 | Understanding EEPROM Programming for 25G and 28G Repeaters and Retimers | PDF | HTML | 2016/1/13 |
設計與開發
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DS280DF810EVM — 28 Gbps 多速率 8 通道重定時器評估模組
DS280DF810EVM 可輕鬆評估 28Gbps 重定時器 DS280DF810。使用者需要透過 Huber+Suhner 1x8 MXP 連接器，為 EVM 提供電源和高速流量。不包含 Huber+Suhner 纜線。
使用者可以透過板載 USB2ANY 連線及 EVM 軟體來評估裝置功能，例如訊號偵測、等化設定、Tx 輸出設定、EEPROM 檔案產生及其他暫存器功能。
TIDA-00427 — 雙埠 100GbE/40GbE/10GbE QSFP28 訊號調節器參考設計
這項經過驗證的參考設計為適用於前連接埠 QSFP28 的訊號調整解決方案，支援兩個符合 100G-CR4/SR4/LR4、40G-CR4/SR4/LR4 及 10G SFF-8431 要求的 100GbE 連接埠。此設計適用於光學和被動/主動銅纜。該設計可實現 Switch ASIC 與前端連接埠 QSFP28 之間的延伸連接，這通常是機架頂端 (ToR) 交換器的最外側連接埠或 QSFP28 線卡的附加夾層實作所必需。此參考設計可讓使用者彈性地從 DS280BR810 中繼器升級至接腳相容的 DS250DF810 重定時器。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| FCCSP (ABW) | 135 | Ultra Librarian |
| FCCSP (ABV) | 135 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。