DS125DF410
- Each Channel Independently Locks to Data Rates from 9.8 to 12.5 Gbps and Submultiples
- Fast Lock Operation Based on Protocol-Select Mode
- Low Latency (~300ps)
- Adaptive Equalization up to 34-dB Boost at 5 GHz
- Adjustable Transmit VOD: 600 to 1300 mVp-p
- Adjustable Transmit De-emphasis to –15 dB
- Typical Power Dissipation (EQ+DFE+CDR+DE): 180 mW/Channel
- Programmable Output Polarity Inversion
- Input Signal Detection, CDR Lock Detection/Indicator
- On-Chip Eye Monitor (EOM), PRBS Generator
- Single 2.5-V ± 5% Power Supply
- SMBus/EEPROM Configuration Modes
- Operating Temperature Range of –40 to 85°C
- WQFN 48-Pin 7-mm x 7-mm Package
- Easy Pin Compatible Upgrade Between Repeater and
Retimers
- DS100RT410 (EQ+CDR+DE): 10.3125 Gbps
- DS100DF410 (EQ+DFE+CDR+DE): 10.3125 Gbps
- DS110RT410 (EQ+CDR+DE): 8.5–11.3 Gbps
- DS110DF410 (EQ+DFE+CDR+DE): 8.5–11.3 Gbps
- DS125RT410 (EQ+CDR+DE): 9.8–12.5 Gbps
- DS125DF410 (EQ+DFE+CDR+DE): 9.8–12.5 Gbps
- DS100BR410 (EQ+DE): Up to 10.3125 Gbps
The DS125DF410 is four channel retimer with integrated signal conditioning. The device includes a fully adaptive Continuous-Time Linear Equalizer (CTLE), self calibrating 5-tap Decision Feedback Equalizer (DFE), Clock and Data Recovery (CDR), and transmit De-Emphasis (DE) driver to enable data transmission over long, lossy and crosstalk-impaired highspeed serial links to achieve BER < 1×10-15.
Each channel can independently lock to data rate from 9.8 to 12.5 Gbps, and associated sub rates (div by 2, 4 and 8) to support a variety of communication protocols. A 25 MHz crystal oscillator clock is used to speed up the CDR lock process. This clock is not used for training the PLL and does not need to be synchronous with the serial data.
The programmable settings can be applied using the SMBus (I2C) interface, or they can be loaded via an external EEPROM. An on-chip eye monitor and a PRBS generator allow real-time measurement of high-speed serial data for system bring-up or field tuning.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | DS125DF410 Low Power Multi-Rate Quad Channel Retimer datasheet (Rev. H) | PDF | HTML | 2018/2/27 | ||
| 應用說明 | Extend reach with Ethernet Redrivers and Retimers for 10G-12.5G Applications (Rev. A) | 2023/1/31 | ||||
| 應用說明 | Implementing TI Retimers on 10G ZR and DWDM SFP+ Optical Links | 2019/4/8 | ||||
| Application brief | DS110DF111,DS125DF111, DS100DF410, DS110DF410, and DS125DF410 Programming Guide | 2019/3/25 | ||||
| 應用說明 | Understanding EEPROM Programming for 10G to 12.5G Retimers | PDF | HTML | 2016/1/13 | |||
| 應用說明 | Selecting TI SigCon Devices for SFF-8431 SFP+ Applications | 2014/5/6 |
設計與開發
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DS125DF410EVM — DS125DF410EVM：具有適應性 EQ、CDR 和 DFE 的 9.8 至 12.5 Gbps 四通道重定時器評估模組
The DS125DF410EVM evaluation board lets you examine the advanced signal conditioning capabilities of the DS125DF410 and DS125RT410 devices using SMAs. The board is controlled by a PC using a USB port and the SigCon Architect GUI.
To use the SigCon Architect GUI to control the device, use the (...)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| WQFN (RHS) | 48 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。