首頁 時鐘與計時 時鐘緩衝器
首頁
時鐘與計時
時鐘緩衝器

CDCM1804

現行

1:3 LVPECL 時鐘緩衝器和 LVCMOS 輸出及可編程分頻器

立即訂購
產品規格表

CDCM1804

現行
產品規格表 立即訂購

產品詳細資料

Number of outputs 3 Additive RMS jitter (typ) (fs) 150 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Output skew (ps) 30 Operating temperature range (°C) -40 to 85 Rating Catalog Output type 1-LVCMOS No of outputs = 3 LVPECL, LVCMOS, LVPECL Input type LVPECL
Number of outputs 3 Additive RMS jitter (typ) (fs) 150 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Output skew (ps) 30 Operating temperature range (°C) -40 to 85 Rating Catalog Output type 1-LVCMOS No of outputs = 3 LVPECL, LVCMOS, LVPECL Input type LVPECL
VQFN (RGE) 24 16 mm² (4 mm × 4 mm)
  • Distributes One Differential Clock Input to Three LVPECL Differential Clock Outputs and One LVCMOS Single-Ended Output
  • Programmable Output Divider for Two LVPECL Outputs and LVCMOS Output
  • Low-Output Skew 15 ps (Typical) for Clock-Distribution Applications for LVPECL Outputs; 1.6-ns Output Skew Between LVCMOS and LVPECL Transitions Minimizing Noise
  • VCC Range 3 V-3.6 V
  • Signaling Rate Up to 800-MHz LVPECL and 200-MHz LVCMOS
  • Differential Input Stage for Wide Common-Mode Range
  • Provides VBB Bias Voltage Output for Single-Ended Input Signals
  • Receiver Input Threshold ±75 mV
  • 24-Terminal QFN Package (4 mm × 4 mm)
  • Accepts Any Differential Signaling: LVDS, HSTL, CML, VML, SSTL-2, and Single-Ended: LVTTL/LVCMOS
  • Distributes One Differential Clock Input to Three LVPECL Differential Clock Outputs and One LVCMOS Single-Ended Output
  • Programmable Output Divider for Two LVPECL Outputs and LVCMOS Output
  • Low-Output Skew 15 ps (Typical) for Clock-Distribution Applications for LVPECL Outputs; 1.6-ns Output Skew Between LVCMOS and LVPECL Transitions Minimizing Noise
  • VCC Range 3 V-3.6 V
  • Signaling Rate Up to 800-MHz LVPECL and 200-MHz LVCMOS
  • Differential Input Stage for Wide Common-Mode Range
  • Provides VBB Bias Voltage Output for Single-Ended Input Signals
  • Receiver Input Threshold ±75 mV
  • 24-Terminal QFN Package (4 mm × 4 mm)
  • Accepts Any Differential Signaling: LVDS, HSTL, CML, VML, SSTL-2, and Single-Ended: LVTTL/LVCMOS

The CDCM1804 clock driver distributes one pair of differential clock inputs to three pairs of LVPECL differential clock outputs Y[2:0] and Y[2:0], with minimum skew for clock distribution. The CDCM1804 is specifically designed for driving 50- transmission lines. Additionally, the CDCM1804 offers a single-ended LVCMOS output Y3. This output is delayed by 1.6 ns over the three LVPECL output stages to minimize noise impact during signal transitions.

The CDCM1804 has three control terminals, S0, S1, and S2, to select different output mode settings. The S[2:0] terminals are 3-level inputs and therefore allow up to 33 = 27 combinations. Additionally, an enable terminal (EN) is provided to disable or enable all outputs simultaneously. The EN terminal is a 3-level input as well and extends the number of settings to 2 × 27 = 54.

The CDCM1804 is characterized for operation from -40°C to 85°C.

For use in single-ended driver applications, the CDCM1804 also provides a VBB output terminal that can be directly connected to the unused input as a common-mode voltage reference.

The CDCM1804 clock driver distributes one pair of differential clock inputs to three pairs of LVPECL differential clock outputs Y[2:0] and Y[2:0], with minimum skew for clock distribution. The CDCM1804 is specifically designed for driving 50- transmission lines. Additionally, the CDCM1804 offers a single-ended LVCMOS output Y3. This output is delayed by 1.6 ns over the three LVPECL output stages to minimize noise impact during signal transitions.

The CDCM1804 has three control terminals, S0, S1, and S2, to select different output mode settings. The S[2:0] terminals are 3-level inputs and therefore allow up to 33 = 27 combinations. Additionally, an enable terminal (EN) is provided to disable or enable all outputs simultaneously. The EN terminal is a 3-level input as well and extends the number of settings to 2 × 27 = 54.

The CDCM1804 is characterized for operation from -40°C to 85°C.

For use in single-ended driver applications, the CDCM1804 also provides a VBB output terminal that can be directly connected to the unused input as a common-mode voltage reference.
filter 尋找其它 時鐘緩衝器
下載 觀看有字幕稿的影片 影片

您可能會感興趣的類似產品

open-in-new 比較替代產品
功能相似於所比較的產品。
CDCP1803 現行 具有可編程分頻器的 1:3 LVPECL 時鐘緩衝器 1:3 LVPECL buffer divider
LMK01000 現行 具 3 個 LVDS 和 5 個 LVPECL 輸出的 1.6-GHz 高性能時脈緩衝器、分頻器和分配器 1:8, LVPECL/LVDS buffer divider
CDCM1802 現行 具有可編程分頻器、LVPECL I/O 和 LVCMOS 輸出時鐘緩衝器 1:2 LVPECL buffer divider

技術文件

找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 2
重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 1:3 LVPECL Clock Buffer & Addl LVCMOS Output & Programmable Divider datasheet (Rev. E) 2005/5/22
應用說明 CDCM1802/CDCM1804 2004/8/4

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

模擬型號

CDCM1804 IBIS Model

SCAC047.ZIP (24 KB) - IBIS 模型
支援產品和硬體
封裝 針腳 CAD 符號、佔位空間與 3D 模型
VQFN (RGE) 24 Ultra Librarian
適用 TI 的評估品項標準條款與條件。

訂購與品質

建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

以英文檢視所有論壇主題

內容係由 TI 和社群貢獻者依「現狀」提供，且不構成 TI 規範。檢視使用條款。

若有關於品質、封裝或訂購 TI 產品的問題，請參閱 TI 支援。​​​​​​​​​​​​​​

影片