ADC12DJ3200QML-SP
Radiation-hardened, QML-V, 300krad, 12-bit dual 3.2GSPS or single 6.4GSPS ADC
ADC12DJ3200QML-SP
- ADC core:
- 12-Bit resolution
- Up to 6.4GSPS in single-channel mode
- Up to 3.2GSPS in dual-channel mode
- Noise floor (no signal, VFS =
1VPP-DIFF):
- Dual-channel mode: –149.5dBFS/Hz
- Single-channel mode: –152.4dBFS/Hz
- Peak noise power ratio (NPR): 45.4dB
- Buffered analog inputs with VCMI of
0V:
- Analog input bandwidth (–3dB): 7GHz
- Usable input frequency range: >10GHz
- Full-scale input voltage (VFS, default): 0.8VPP
- Noiseless aperture delay (tAD) adjustment:
- Precise sampling control: 19fs step size
- Temperature and voltage invariant delays
- Easy-to-use synchronization features
- Automatic SYSREF timing calibration
- Timestamp for sample marking
- JESD204B subclass-1 compliant interface:
- Maximum lane rate: 12.8Gbps
- Up to 16 lanes allows reduced lane rate
- Digital down-converters in dual-channel mode:
- Real output: DDC bypass or 2x decimation
- Complex output: 4x, 8x, or 16x decimation
- Radiation performance:
- Total Ionizing Dose (TID): 300krad (Si)
- Single Event Latchup (SEL): 120MeV-cm2/mg
- Single Event Upset (SEU) immune registers
- Power consumption: 3W
The ADC12DJ3200QML-SP device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from dc to above 10GHz. In dual-channel mode, the ADC12DJ3200QML-SP can sample up to 3200MSPS. In single-channel mode, the device can sample up to 6400MSPS. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3dB) of 7GHz, with usable frequencies exceeding the –3dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.
The ADC12DJ3200QML-SP uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multidevice synchronization. The serial output lanes support up to 12.8Gbps, and can be configured to trade off bit rate and number of lanes. Innovative synchronization features, including noiseless aperture delay (tAD) adjustment and SYSREF windowing, simplify system design for synthetic aperture radar (SAR) and phased-array MIMO communications. Optional digital down converters (DDCs) in dual-channel mode allow for reduction in interface rate (real and complex decimation modes) and digital mixing of the signal (complex decimation modes only).
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | ADC12DJ3200QML-SP 6.4GSPS, Single-Channel or 3.2GSPS, Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC) datasheet (Rev. C) | PDF | HTML | 2025/3/21 | ||
| * | 輻射及可靠性報告 | ADC12DJ3200QML-SP - Single-Event Effects (SEE) Radiation Test Report | 2020/8/3 | |||
| * | 輻射及可靠性報告 | Analysis of Low Dose Rate Effects on Parasitic Bipolar Structures in CMOS Proces | 2012/5/4 | |||
| * | SMD | ADC12DJ3200QML-SP SMD ADC12DJ3200QML-SP SMD 5962-18209 | 2020/8/4 | |||
| 選擇指南 | TI Space Products (Rev. L) | 2026/3/27 | ||||
| Application brief | DLA Approved Optimizations for QML Products (Rev. C) | PDF | HTML | 2025/6/17 | |||
| 應用說明 | Heavy Ion Orbital Environment Single-Event Effects Estimations (Rev. B) | PDF | HTML | 2025/6/10 | |||
| 更多文件說明 | TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. B) | 2025/2/20 | ||||
| 應用說明 | Single-Event Effects Confidence Interval Calculations (Rev. A) | PDF | HTML | 2022/10/19 | |||
| 技術文章 | How SHP in plastic packaging addresses 3 key space application design challenges | PDF | HTML | 2022/10/17 |
設計與開發
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ADC12DJ3200EVMCVAL — ADC12DJ3200QML-SP 評估模組
TI204C-IP — Request for JESD204 rapid design IP
JESD204 快速設計 IP 被設計用於幫助 FPGA 工程師快速實現可運作的 JESD204 系統，從而加速開發過程。該 IP 的架構設計使得下游數位處理和其他應用邏輯能夠隔離於 JESD204 通訊協定的大多數性能和時序關鍵約束之外。該 IP 能夠幫助設計人員減少韌體開發時間並簡化 FPGA 的整合。
JESD204 快速設計 IP 無需權利金，用於 TI 高速資料轉換器。TI 將協助使用者配置初始連結，針對特定 FPGA 平台與 TI 資料轉換器 JMODE 之間的使用進行自訂。TI 將在 IP 測試完成並準備部署後，透過安全下載連結提供 IP。
JESD204 快速設計 IP 支援下列 (...)
SLVC806 — Xilinx AlphaData Demo
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| CCGA-FC (NWE) | 196 | Ultra Librarian |
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