홈 마이크로컨트롤러(MCU) 및 프로세서 마이크로프로세서 및 DSP 오디오 및 레이더 DSP SoC
홈
마이크로컨트롤러(MCU) 및 프로세서
마이크로프로세서 및 DSP
오디오 및 레이더 DSP SoC

TMS320C6711D

활성

C67x 부동 소수점 DSP - 최대 250MHz, McBSP, 32비트 EMIFA

지금 주문하기
데이터 시트
정오표

TMS320C6711D

활성
데이터 시트 지금 주문하기

제품 상세 정보

CPU 32-/64-bit Operating system DSP/BIOS Rating Catalog Operating temperature range (°C) -40 to 105
CPU 32-/64-bit Operating system DSP/BIOS Rating Catalog Operating temperature range (°C) -40 to 105
BGA (ZDP) 272 729 mm² 27 x 27 PBGA (GDP) 272 729 mm² 27 x 27 PBGA (ZDP) 272 See data sheet
  • Excellent-Price/Performance Floating-Point Digital Signal Processor (DSP):
      TMS320C6711D
    • Eight 32-Bit Instructions/Cycle
    • 167-, 200-, 250-MHz Clock Rates
    • 6-, 5-, 4-ns Instruction Cycle Time
    • 1000, 1200, 1500 MFLOPS
  • Advanced Very Long Instruction Word (VLIW) C67x™ DSP Core
    • Eight Highly Independent Functional Units:
      • Four ALUs (Floating- and Fixed-Point)
      • Two ALUs (Fixed-Point)
      • Two Multipliers (Floating- and Fixed-Point)
    • Load-Store Architecture With 32 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Hardware Support for IEEE Single-Precision and Double-Precision Instructions
    • Byte-Addressable (8-, 16-, 32-Bit Data)
    • 8-Bit Overflow Protection
    • Saturation
    • Bit-Field Extract, Set, Clear
    • Bit-Counting
    • Normalization
  • L1/L2 Memory Architecture
    • 32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped)
    • 32K-Bit (4K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation)
  • Device Configuration
    • Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot
    • Endianness: Little Endian, Big Endian
  • Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)
  • 32-Bit External Memory Interface (EMIF)
    • Glueless Interface to Asynchronous Memories: SRAM and EPROM
    • Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
    • 256M-Byte Total Addressable External Memory Space
  • 16-Bit Host-Port Interface (HPI)
  • Two Multichannel Buffered Serial Ports (McBSPs)
    • Direct Interface to T1/E1, MVIP, SCSA Framers
    • ST-Bus-Switching Compatible
    • Up to 256 Channels Each
    • AC97-Compatible
    • Serial-Peripheral-Interface (SPI) Compatible (Motorola™)
  • Two 32-Bit General-Purpose Timers
  • Flexible Software Configurable PLL-Based Clock Generator Module
  • A Dedicated General-Purpose Input/Output (GPIO) Module With 5 Pins
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • 272-Pin Ball Grid Array (BGA) Package (GDP and ZDP Suffixes)
  • CMOS Technology
    • 0.13-µm/6-Level Copper Metal Process
  • 3.3-V I/O, 1.4-V Internal (-250)
  • 3.3-V I/O, 1.20-V Internal

TMS320C67x and C67x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
All trademarks are the property of their respective owners.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
These values are compatible with existing 1.26V designs.
TMS320C6000 is a trademark of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
Throughout the remainder of this document, the TMS320C6711D shall be referred to as its individual full device part number or abbreviated as C6711D or 11D.
  • Excellent-Price/Performance Floating-Point Digital Signal Processor (DSP):
      TMS320C6711D
    • Eight 32-Bit Instructions/Cycle
    • 167-, 200-, 250-MHz Clock Rates
    • 6-, 5-, 4-ns Instruction Cycle Time
    • 1000, 1200, 1500 MFLOPS
  • Advanced Very Long Instruction Word (VLIW) C67x™ DSP Core
    • Eight Highly Independent Functional Units:
      • Four ALUs (Floating- and Fixed-Point)
      • Two ALUs (Fixed-Point)
      • Two Multipliers (Floating- and Fixed-Point)
    • Load-Store Architecture With 32 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Hardware Support for IEEE Single-Precision and Double-Precision Instructions
    • Byte-Addressable (8-, 16-, 32-Bit Data)
    • 8-Bit Overflow Protection
    • Saturation
    • Bit-Field Extract, Set, Clear
    • Bit-Counting
    • Normalization
  • L1/L2 Memory Architecture
    • 32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped)
    • 32K-Bit (4K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation)
  • Device Configuration
    • Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot
    • Endianness: Little Endian, Big Endian
  • Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)
  • 32-Bit External Memory Interface (EMIF)
    • Glueless Interface to Asynchronous Memories: SRAM and EPROM
    • Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
    • 256M-Byte Total Addressable External Memory Space
  • 16-Bit Host-Port Interface (HPI)
  • Two Multichannel Buffered Serial Ports (McBSPs)
    • Direct Interface to T1/E1, MVIP, SCSA Framers
    • ST-Bus-Switching Compatible
    • Up to 256 Channels Each
    • AC97-Compatible
    • Serial-Peripheral-Interface (SPI) Compatible (Motorola™)
  • Two 32-Bit General-Purpose Timers
  • Flexible Software Configurable PLL-Based Clock Generator Module
  • A Dedicated General-Purpose Input/Output (GPIO) Module With 5 Pins
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • 272-Pin Ball Grid Array (BGA) Package (GDP and ZDP Suffixes)
  • CMOS Technology
    • 0.13-µm/6-Level Copper Metal Process
  • 3.3-V I/O, 1.4-V Internal (-250)
  • 3.3-V I/O, 1.20-V Internal

TMS320C67x and C67x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
All trademarks are the property of their respective owners.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
These values are compatible with existing 1.26V designs.
TMS320C6000 is a trademark of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
Throughout the remainder of this document, the TMS320C6711D shall be referred to as its individual full device part number or abbreviated as C6711D or 11D.

The TMS320C67x™ DSPs (including the TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D devices) compose the floating-point DSP family in the TMS320C6000™ DSP platform. The C6711, C6711B, C6711C, and C6711D devices are based on the high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications.

With performance of up to 1200 million floating-point operations per second (MFLOPS) at a clock rate of 200 MHz or up to 1500 MFLOPS at a clock rate of 250 MHz, the C6711D device also offers cost-effective solutions to high-performance DSP programming challenges. The C6711D DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The C6711D can produce two MACs per cycle for a total of 400 MMACS.

The C6711D DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The C6711D device uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 512-Kbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM and asynchronous peripherals.

The C6711D has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

The TMS320C67x™ DSPs (including the TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D devices) compose the floating-point DSP family in the TMS320C6000™ DSP platform. The C6711, C6711B, C6711C, and C6711D devices are based on the high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications.

With performance of up to 1200 million floating-point operations per second (MFLOPS) at a clock rate of 200 MHz or up to 1500 MFLOPS at a clock rate of 250 MHz, the C6711D device also offers cost-effective solutions to high-performance DSP programming challenges. The C6711D DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The C6711D can produce two MACs per cycle for a total of 400 MMACS.

The C6711D DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The C6711D device uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 512-Kbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM and asynchronous peripherals.

The C6711D has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.
filter 기타 오디오 및 레이더 DSP SoC 찾기
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기술 자료

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상위 문서 유형 직함 형식 옵션 날짜
* Data sheet TMS320C6711D Floating-Point Digital Signal Processor datasheet (Rev. B) 2006/06/30
* Errata TMS320C6711/C6711B/C6711C/C6711D DSPs Errata-Revs 1.0, 1.1, 1.2, 1.3, 2.0, 2.1) (Rev. P) 2005/08/12
Application note How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A) PDF | HTML 2021/05/19
Application note Introduction to TMS320C6000 DSP Optimization 2011/10/06
User guide TMS320C6000 DSP Peripherals Overview Reference Guide (Rev. Q) 2009/07/02
Application note Thermal Considerations for the DM64xx, DM64x, and C6000 Devices 2007/05/20
User guide TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide (Rev. E) 2007/04/11
User guide TMS320C6000 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (Rev. G) 2006/12/14
User guide TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (Rev. C) 2006/11/15
User guide TMS320C6000 DSP Host-Post Interface (HPI) Reference Guide (Rev. C) 2006/01/01
Application note Migrating From TMS320C6211B/C6711/C6711B/C6711C to TMS320C6711D (Rev. H) 2005/11/10
User guide TMS320C6000 DSP Power-Down Logic and Modes Reference Guide (Rev. C) 2005/03/01
User guide TMS320C6000 DSP 32-bit Timer Reference Guide (Rev. B) 2005/01/25
User guide TMS320C6000 DSP Software-Programmable Phase-Locked Loop (PLL) Controller RG (Rev. C) 2004/08/02
User guide TMS320C621x/C671x DSP Two Level Internal Memory Reference Guide (Rev. B) 2004/06/08
Application note TMS320C6711D, C6712D, C6713B Power Consumption Summary (Rev. A) 2004/05/31
User guide TMS320C6000 DSP General-Purpose Input/Output (GPIO) Reference Guide (Rev. A) 2004/03/25
Application note TMS320C6000 EDMA IO Scheduling and Performance 2004/03/05
Application note TMS320C621x/671x EDMA Performance Data 2004/03/05
Application note TMS320C621x/TMS320C671x EDMA Architecture 2004/03/05

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XDS560v2는 디버그 프로브의 XDS560™ 제품군 중 최고의 성능을 가진 제품으로, 기존의 JTAG 표준(IEEE1149.1)과 cJTAG(IEEE1149.7)를 모두 지원합니다. SWD(직렬 와이어 디버그)는 지원하지 않습니다.

모든 XDS 디버그 프로브는 ETB(Embedded Trace Buffer)를 특징으로 하는 모든 ARM 및 DSP 프로세서에서 코어 및 시스템 추적을 지원합니다. 핀을 통한 추적의 경우 XDS560v2 PRO TRACE가 필요합니다.

XDS560v2는 MIPI HSPT 60핀 커넥터(TI 14핀, (...)

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The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

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Lauterbach‘s TRACE32® tools are a suite of leading-edge hardware and software components that enables developers to analyze, optimize and certify all kinds of single- or multi-core Digital Signal processors (DSPs) which are a popular choice for audio and video processing as well as radar data (...)

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AEC-AER — Acoustic echo cancellation/removal for TI C64x+, C674x, C55x and Cortex®-A8 processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

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드라이버 또는 라이브러리

C64X-DSPLIB — Download TMS320C64x DSP Library

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)

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드라이버 또는 라이브러리

C67X-DSPLIB — Download TMS320C67x DSP Library

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)

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드라이버 또는 라이브러리

C67X-MATHLIB — DSP Math Library for C67x Floating Point Devices

The Texas Instruments math library is an optimized floating-point math function library for C programmers using TI floating point devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By using these routines instead (...)
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드라이버 또는 라이브러리

FAXLIB — FAX library (FAXLIB) for C66x, C64x+ and C55x processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

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드라이버 또는 라이브러리

VOLIB — Voice library (VoLIB) for C66x, C64x+ and C55x processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

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CCSTUDIO — Code Composer Studio integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize embedded applications. Code Composer Studio is available across Windows®, Linux® and macOS® platforms.

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C6711D GDP BSDL Model

SPRM216.ZIP (6 KB) - BSDL Model
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C6711D GDP IBIS Model

SPRM145.ZIP (69 KB) - IBIS Model
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BGA (ZDP) 272 Ultra Librarian
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PBGA (ZDP) 272 Ultra Librarian
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