제품 상세 정보

Protocols Analog Configuration 1:1 SPST Number of channels 8 Bandwidth (MHz) 500 Ron (typ) (mΩ) 4000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 5.5 Supply current (typ) (µA) 1000 Operating temperature range (°C) -40 to 85 ESD CDM (kV) 1 Input/output continuous current (max) (mA) 64 COFF (typ) (pF) 3.5 CON (typ) (pF) 9 OFF-state leakage current (max) (µA) 1 Ron (max) (mΩ) 9000 VIH (min) (V) 1.7 VIL (max) (V) 0.8 Rating Catalog
Protocols Analog Configuration 1:1 SPST Number of channels 8 Bandwidth (MHz) 500 Ron (typ) (mΩ) 4000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 5.5 Supply current (typ) (µA) 1000 Operating temperature range (°C) -40 to 85 ESD CDM (kV) 1 Input/output continuous current (max) (mA) 64 COFF (typ) (pF) 3.5 CON (typ) (pF) 9 OFF-state leakage current (max) (µA) 1 Ron (max) (mΩ) 9000 VIH (min) (V) 1.7 VIL (max) (V) 0.8 Rating Catalog
TSSOP (PW) 20 41.6 mm² (6.5 mm × 6.4 mm) TVSOP (DGV) 20 32 mm² (5 mm × 6.4 mm) SSOP (DBQ) 20 51.9 mm² (8.65 mm × 6 mm) VQFN (RGY) 20 15.75 mm² (4.5 mm × 3.5 mm)
  • High-Bandwidth Data Path (Up to 500 MHz)
  • Equivalent to IDTQS3VH384 Device
  • 5-V Tolerant I/Os with Device Powered-Up or Powered-Down
  • Low and Flat ON-State Resistance (ron) Characteristics Over Operating Range (ron = 4 Typical)
  • Rail-to-Rail Switching on Data I/O Ports
    • 0- to 5-V Switching With 3.3-V VCC
    • 0- to 3.3-V Switching With 2.5-V VCC
  • Bidirectional Data Flow, With Near-Zero Propagation Delay
  • Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 3.5 pF Typical)
  • Fast Switching Frequency (fOE\ = 20 MHz Max)
  • Data and Control Inputs Provide Undershoot Clamp Diodes
  • Low Power Consumption (ICC = 1 mA Typical)
  • VCC Operating Range From 2.3 V to 3.6 V
  • Data I/Os Support 0 to 5-V Signaling Levels (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
  • Control Inputs Can be Driven by TTL or 5-V/3.3-V CMOS Outputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Supports Both Digital and Analog Applications: PCI Interface, Differential Signal Interface, Memory Interleaving, Bus Isolation, Low-Distortion Signal Gating

For additional information regarding the performance characteristics of the CB3Q family, refer to the TI application report, CBT-C, CB3T, and CB3Q Signal-Switch Families, literature number SCDA008.

  • High-Bandwidth Data Path (Up to 500 MHz)
  • Equivalent to IDTQS3VH384 Device
  • 5-V Tolerant I/Os with Device Powered-Up or Powered-Down
  • Low and Flat ON-State Resistance (ron) Characteristics Over Operating Range (ron = 4 Typical)
  • Rail-to-Rail Switching on Data I/O Ports
    • 0- to 5-V Switching With 3.3-V VCC
    • 0- to 3.3-V Switching With 2.5-V VCC
  • Bidirectional Data Flow, With Near-Zero Propagation Delay
  • Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 3.5 pF Typical)
  • Fast Switching Frequency (fOE\ = 20 MHz Max)
  • Data and Control Inputs Provide Undershoot Clamp Diodes
  • Low Power Consumption (ICC = 1 mA Typical)
  • VCC Operating Range From 2.3 V to 3.6 V
  • Data I/Os Support 0 to 5-V Signaling Levels (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
  • Control Inputs Can be Driven by TTL or 5-V/3.3-V CMOS Outputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Supports Both Digital and Analog Applications: PCI Interface, Differential Signal Interface, Memory Interleaving, Bus Isolation, Low-Distortion Signal Gating

For additional information regarding the performance characteristics of the CB3Q family, refer to the TI application report, CBT-C, CB3T, and CB3Q Signal-Switch Families, literature number SCDA008.

The SN74CB3Q3245 is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q3245 provides an optimized interface solution ideally suited for broadband communications, networking, and data-intensive computing systems.

The SN74CB3Q3245 is organized as an 8-bit bus switch with a single output-enable (OE\) input. When OE\ is low, the bus switch is ON and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE\ is high, the bus switch is OFF and a high-impedance state exists between the A and B ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging current backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74CB3Q3245 is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q3245 provides an optimized interface solution ideally suited for broadband communications, networking, and data-intensive computing systems.

The SN74CB3Q3245 is organized as an 8-bit bus switch with a single output-enable (OE\) input. When OE\ is low, the bus switch is ON and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE\ is high, the bus switch is OFF and a high-impedance state exists between the A and B ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging current backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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* 데이터 시트 SN74CB3Q3245 datasheet (Rev. B) 2003. 11. 20
애플리케이션 노트 Selecting the Correct Texas Instruments Signal Switch (Rev. E) PDF | HTML 2022. 6. 2
애플리케이션 노트 Multiplexers and Signal Switches Glossary (Rev. B) PDF | HTML 2021. 12. 1
Application brief Eliminate Power Sequencing with Powered-off Protection Signal Switches (Rev. C) PDF | HTML 2021. 1. 6

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시뮬레이션 모델

SN74CB3Q3245 IBIS Model (Rev. A)

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TIDA-00299 — EtherCAT 슬레이브 및 다중 프로토콜 산업 이더넷 레퍼런스 설계

이 레퍼런스 설계는 애플리케이션 프로세서에 대한 SPI 인터페이스를 지원하는 비용 최적화된 고 EMC 내성 EtherCAT 슬레이브(듀얼 포트)를 구현합니다. 이 하드웨어 설계는 AMIC110 산업용 통신 프로세서를 사용하여 멀티 프로토콜 산업용 이더넷 및 필드 버스를 지원할 수 있습니다. 이 설계는 5V 공급 장치 하나에서 실행되며, PMIC 한 개가 필요한 온보드 레일을 모두 생성합니다. EtherCAT 슬레이브 스택은 AMIC110 또는 SPI(직렬 주변 기기 인터페이스)를 사용하여 애플리케이션 프로세서에서 실행할 수 (...)

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TSSOP (PW) 20 Ultra Librarian
TVSOP (DGV) 20 Ultra Librarian
SSOP (DBQ) 20 Ultra Librarian
VQFN (RGY) 20 Ultra Librarian

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