SN74AUP2G08

Name: SN74AUP2G08
Brand: TI
SKU: SN74AUP2G08
Price: 0.15 USD

활성

2채널, 2입력, 0.8V~3.6V 저전력(< 1uA) AND 게이트

지금 주문

데이터 시트

document-pdfAcrobat SN74AUP2G08 Low-Power Dual 2-Input Positive-AND Gate datasheet (Rev. F) (영어) PDF | HTML

SN74AUP2G08

활성

데이터 시트

지금 주문

제품 상세 정보

Technology family

AUP

Supply voltage (min) (V)

0.8

Supply voltage (max) (V)

3.6

Number of channels

Inputs per channel

IOL (max) (mA)

IOH (max) (mA)

-4

Input type

Standard CMOS

Output type

Push-Pull

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Data rate (max) (Mbps)

100

Rating

Catalog

Operating temperature range (°C)

-40 to 125

Technology family

AUP

Supply voltage (min) (V)

0.8

Supply voltage (max) (V)

3.6

Number of channels

Inputs per channel

IOL (max) (mA)

IOH (max) (mA)

-4

Input type

Standard CMOS

Output type

Push-Pull

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Data rate (max) (Mbps)

100

Rating

Catalog

Operating temperature range (°C)

-40 to 125

DSBGA (YFP)

1.8 mm² 1 x 1.8

DSBGA (YZP)

2.8125 mm² 2.25 x 1.25

UQFN (RSE)

2.25 mm² 1.5 x 1.5

VSSOP (DCU)

6.2 mm² 2 x 3.1

X2SON (DQE)

1.4 mm² 1.4 x 1

Wide operating VCC range of 0.8V to 3.6V
Low static-power consumption (ICC = 0.9µA max)
Low dynamic-power consumption (Cpd = 4.3pF typ at 3.3V)
Low noise – overshoot and undershoot <10% of VCC
Ioff supports partial-power-down mode operation
Schmitt-trigger action allows slow input transition and better switching noise immunity at the input (Vhys = 250mV Typ at 3.3V)
3.6V I/O tolerant to support mixed-mode signal operation
tpd = 5.9ns max at 3.3V
Latch-up performance exceeds 100mA per JESD 78, Class II

Wide operating VCC range of 0.8V to 3.6V
Low static-power consumption (ICC = 0.9µA max)
Low dynamic-power consumption (Cpd = 4.3pF typ at 3.3V)
Low noise – overshoot and undershoot <10% of VCC
Ioff supports partial-power-down mode operation
Schmitt-trigger action allows slow input transition and better switching noise immunity at the input (Vhys = 250mV Typ at 3.3V)
3.6V I/O tolerant to support mixed-mode signal operation
tpd = 5.9ns max at 3.3V
Latch-up performance exceeds 100mA per JESD 78, Class II

This dual 2-input positive-AND gate is designed for 0.8V to 3.6V VCC operation and performs the Boolean function Y = A ● B in positive logic.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when VCC = 0V, preventing damaging current backflow through the device when it is powered down.

This dual 2-input positive-AND gate is designed for 0.8V to 3.6V VCC operation and performs the Boolean function Y = A ● B in positive logic.

filter

기타 AND 게이트 찾기

다운로드 스크립트와 함께 비디오 보기 동영상

관심 가지실만한 유사 제품

open-in-new

대안 비교

비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀

SN74LVC2G08

활성

2채널 2입력 1.65V~5.5V 32mA 드라이브 강도 AND 게이트 Larger voltage range (1.65V to 5.5V), higher drive average drive strength (24mA)

기술 자료

star

=TI에서 선정한 이 제품의 인기 문서

검색된 결과가 없습니다. 검색어를 지우고 다시 시도하십시오.

6개 모두 보기

	유형	직함		날짜
*	Data sheet	SN74AUP2G08 Low-Power Dual 2-Input Positive-AND Gate datasheet (Rev. F)	PDF \| HTML	2025/05/18
	Application brief	Understanding Schmitt Triggers (Rev. B)	PDF \| HTML	2025/04/17
	Selection guide	Little Logic Guide 2018 (Rev. G)		2018/07/06
	Application note	How to Select Little Logic (Rev. A)		2016/07/26
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		2004/07/08
	Selection guide	Logic Guide (Rev. AC)	PDF \| HTML	1994/06/01