SN65LVDS33-EP

활성

EP(Enhanced Product) 고속 차동 리시버

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document-pdfAcrobat SN65LVDS33-EP High-Speed Differential Receivers datasheet (Rev. B) (영어)

SN65LVDS33-EP

활성

데이터 시트

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제품 상세 정보

Function

Receiver

Protocols

LVDS

Number of transmitters

0

Number of receivers

4

Signaling rate (Mbps)

400

Input signal

CMOS, ECL, LVCMOS, LVDS, LVECL, LVPECL, PECL

Output signal

LVTTL

Rating

HiRel Enhanced Product

Operating temperature range (°C)

-55 to 125

Function

Receiver

Protocols

LVDS

Number of transmitters

0

Number of receivers

4

Signaling rate (Mbps)

400

Input signal

CMOS, ECL, LVCMOS, LVDS, LVECL, LVPECL, PECL

Output signal

LVTTL

Rating

HiRel Enhanced Product

Operating temperature range (°C)

-55 to 125

SOIC (D)

16

59.4 mm² (9.9 mm × 6 mm)

Controlled Baseline — One Assembly/Test Site, One Fabrication Site
Extended Temperature Performance of Up to -55°C to 125°C
Enhanced Diminishing Manufacturing Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree⁽¹⁾
400-Mbps Signaling Rate⁽²⁾ and 200-Mxfr/s Data Transfer Rate
Operates With a Single 3.3-V Supply
-4-V to 5-V Common-Mode Input Voltage Range
Differential Input Thresholds < ±50 mV With 50 mV of Hysteresis Over Entire Common-Mode Input Voltage Range
Integrated 110- Line Termination Resistors On LVDT Products
Complies With TIA/EIA-644 (LVDS)
Active Failsafe Assures a High-Level Output With No Input
Bus-Pin ESD Protection Exceeds 15-kV HBM
Input Remains High-Impedance On Power Down
TTL Inputs Are 5-V Tolerant
Pin-Compatible With the AM26LS32, SN65LVDS32B, µA9637, SN65LVDS9637B

⁽¹⁾ Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
⁽²⁾ The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).

Controlled Baseline — One Assembly/Test Site, One Fabrication Site
Extended Temperature Performance of Up to -55°C to 125°C
Enhanced Diminishing Manufacturing Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree⁽¹⁾
400-Mbps Signaling Rate⁽²⁾ and 200-Mxfr/s Data Transfer Rate
Operates With a Single 3.3-V Supply
-4-V to 5-V Common-Mode Input Voltage Range
Differential Input Thresholds < ±50 mV With 50 mV of Hysteresis Over Entire Common-Mode Input Voltage Range
Integrated 110- Line Termination Resistors On LVDT Products
Complies With TIA/EIA-644 (LVDS)
Active Failsafe Assures a High-Level Output With No Input
Bus-Pin ESD Protection Exceeds 15-kV HBM
Input Remains High-Impedance On Power Down
TTL Inputs Are 5-V Tolerant
Pin-Compatible With the AM26LS32, SN65LVDS32B, µA9637, SN65LVDS9637B

⁽¹⁾ Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
⁽²⁾ The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).

This family of four LVDS data line receivers offers the widest common-mode input voltage range in the industry. These receivers provide an input voltage range specification compatible with a 5-V PECL signal as well as an overall increased ground-noise tolerance. They are in industry standard footprints with integrated termination as an option.

Precise control of the differential input voltage thresholds allows for inclusion of 50 mV of input voltage hysteresis to improve noise rejection on slowly changing input signals. The input thresholds are still no more than +50 mV over the full input common-mode voltage range.

The high-speed switching of LVDS signals usually necessitates the use of a line impedance matching resistor at the receiving-end of the cable or transmission media. The SN65LVDT series of receivers eliminates this external resistor by integrating it with the receiver. The nonterminated SN65LVDS series is also available for multidrop or other termination circuits.

The receivers can withstand ±15-kV human-body model (HBM) and ±600-V machine model (MM) electrostatic discharges to the receiver input pins with respect to ground without damage. This provides reliability in cabled and other connections where potentially damaging noise is always a threat.

The receivers also include a (patent pending) failsafe circuit that provides a high-level output within 600 ns after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or powered-down transmitters. The failsafe circuit prevents noise from being received as valid data under these fault conditions. This feature may also be used for Wired-Or bus signaling. See The Active Failsafe Feature of the SN65LVDS32B application note.

The intended application and signaling technique of these devices is point-to-point baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

The SN65LVDS33-EP is characterized for operation from -55°C to 125°C.

This family of four LVDS data line receivers offers the widest common-mode input voltage range in the industry. These receivers provide an input voltage range specification compatible with a 5-V PECL signal as well as an overall increased ground-noise tolerance. They are in industry standard footprints with integrated termination as an option.

Precise control of the differential input voltage thresholds allows for inclusion of 50 mV of input voltage hysteresis to improve noise rejection on slowly changing input signals. The input thresholds are still no more than +50 mV over the full input common-mode voltage range.

The high-speed switching of LVDS signals usually necessitates the use of a line impedance matching resistor at the receiving-end of the cable or transmission media. The SN65LVDT series of receivers eliminates this external resistor by integrating it with the receiver. The nonterminated SN65LVDS series is also available for multidrop or other termination circuits.

The receivers can withstand ±15-kV human-body model (HBM) and ±600-V machine model (MM) electrostatic discharges to the receiver input pins with respect to ground without damage. This provides reliability in cabled and other connections where potentially damaging noise is always a threat.

The receivers also include a (patent pending) failsafe circuit that provides a high-level output within 600 ns after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or powered-down transmitters. The failsafe circuit prevents noise from being received as valid data under these fault conditions. This feature may also be used for Wired-Or bus signaling. See The Active Failsafe Feature of the SN65LVDS32B application note.

The intended application and signaling technique of these devices is point-to-point baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

The SN65LVDS33-EP is characterized for operation from -55°C to 125°C.

filter

기타 LVDS, M-LVDS 및 PECL IC 찾기

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open-in-new

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SN65LVDS31-EP

활성

EP(Enhanced Product) 쿼드 LVDS 트랜스미터 Line Driver variant

기술 자료

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6개 모두 보기

상위 문서	유형	직함	날짜
*	데이터 시트	SN65LVDS33-EP High-Speed Differential Receivers datasheet (Rev. B)	2007. 4. 19
*	방사능 및 안정성 보고서	SN65LVDS33MDREP Reliability Report	2013. 9. 6
*	VID	SN65LVDS33-EP VID V6205614	2016. 6. 21
	Application brief	LVDS to Improve EMC in Motor Drives	2018. 9. 27
	Application brief	How Far, How Fast Can You Operate LVDS Drivers and Receivers?	2018. 8. 3
	Application brief	How to Terminate LVDS Connections with DC and AC Coupling	2018. 5. 16

설계 및 개발

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평가 보드

SN65LVDS31-33EVM — SN65LVDS31 및 SN65LVDS33용 평가 모듈

TI offers a series of low-voltage differential signaling (LVDS) evaluation modules (EVMs) designed for analysis of the electrical characteristics of LVDS drivers and receivers. Four unique EVMs are available to evaluate the different classes of LVDS devices offered by TI.

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