DS90UH927Q-Q1
- Integrated HDCP Cipher Engine with On-Chip Key
Storage - Bidirectional Control Channel Interface with I2C
Compatible Serial Control Bus - Low EMI FPD-Link Video Input
- Supports High Definition (720p) Digital Video
Format - 5-MHz to 85-MHz PCLK Supported
- RGB888 + VS, HS, DE and I2S Audio Supported
- Up to 4 I2S Digital Audio Inputs for Surround
Sound Applications - 4 Bidirectional GPIO Channels with 2 Dedicated
Pins - Single 3.3-V Supply with 1.8-V or 3.3-V
Compatible LVCMOS I/O Interface - AC-Coupled STP Interconnect up to 10 Meters
- DC-Balanced & Scrambled Data with Embedded
Clock - Supports HDCP Repeater Application
- Internal Pattern Generation
- Low Power Modes Minimize Power Dissipation
- Automotive Grade Product: AEC-Q100 Grade 2
Qualified - > 8-kV HBM and ISO 10605 ESD Rating
- Backward Compatible Modes
The DS90UH927Q-Q1 serializer, in conjunction with a DS90UH928Q-Q1 or DS90UH926Q-Q1 deserializer, provides a solution for secure distribution of content-protected digital video within automotive entertainment systems. This chipset translates a FPD-Link video interface into a single-pair high-speed serialized interface. The digital video data is protected using the industry standard High-Bandwidth Digital Content Protection (HDCP) copy protection scheme. The FPD-Link III serial bus scheme supports full duplex, high speed forward channel data transmission and low-speed back channel communication over a single differential link. Consolidation of audio, video, and control data over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.
The DS90UH927Q-Q1 serializer embeds the clock, content protects the data payload, and level shifts the signals to high-speed differential signaling. Up to 24 RGB data bits are serialized along with three video control signals, and up to four I2S data inputs.
The FPD-Link data interface allows for easy interfacing with data sources while also minimizing EMI and bus width. EMI on the high-speed FPD-Link III bus is minimized using low voltage differential signaling, data scrambling and randomization, and dc-balancing.
The HDCP cipher engine is implemented in both the serializer and deserializer. HDCP keys are stored in on-chip memory.
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기술 자료
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 |
|---|---|---|---|---|---|
| * | 데이터 시트 | DS90UH927Q-Q1 5-MHz to 85-MHz 24-Bit Color FPD-Link III Serializer with HDCP datasheet (Rev. C) | PDF | HTML | 2015. 2. 2 | |
| 애플리케이션 노트 | Using the I2S Audio Interface of DS90Ux92x FPD-Link III Devices | 2013. 5. 4 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
DS90UH927QEVM — DS90UH927Q-Q1 5MHz-85MHz FPD-Link III 시리얼라이저 평가 모듈
The Texas Instruments DS90UB927QEVM evaluation module (EVM) helps system designers evaluate the operation and performance of the DS90UB927Q 5MHz-85MHz FPD-Link III Serializer (SER). The device translates four FPD-Link (I) compatible LVDS data input pairs and one LVDS clock into a high-speed (...)
ALP — Analog LaunchPad Framework Utility
ALP-PROFILE-UPDATE — Analog LaunchPad Profile Update Software
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| WQFN (RTA) | 40 | Ultra Librarian |
주문 및 품질
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