DS90UH925Q-Q1
- Integrated HDCP Cipher Engine with On-chip Key
Storage - Bidirectional Control Interface Channel Interface
with I2C Compatible Serial Control Bus - Supports High Definition (720p) Digital Video
Format - RGB888 + VS, HS, DE and I2S Audio Supported
- 5 to 85 MHz PCLK Supported
- Single 3.3V Operation with 1.8 V or 3.3 V Compatible
LVCMOS I/O Interface - AC-coupled STP Interconnect up to 10 meters
- Parallel LVCMOS Video Inputs
- DC-balanced & Scrambled Data with Embedded
Clock - HDCP Content Protected
- Supports HDCP Repeater Application
- Internal Pattern Generation
- Low Power Modes Minimize Power Dissipation
- Automotive Grade Product: AEC-Q100 Grade 2 Qualified
- > 8k V HBM and ISO 10605 ESD rating
- Backward Compatible Modes
The DS90UH925Q-Q1 serializer, in conjunction with the DS90UH926Q-Q1 deserializer, provides a solution for secure distribution of content-protected digital video within automotive entertainment systems. This chipset translates a parallel RGB Video Interface into a single pair high-speed serialized interface. The digital video data is protected using the industry standard HDCP copy protection scheme. The serial bus scheme, FPD-Link III, supports video and audio data transmission and full duplex control including I2C communication over a single differential link. Consolidation of video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.
The DS90UH925Q-Q1 serializer embeds the clock, content protects the data payload, and level shifts the signals to high-speed low voltage differential signaling. Up to 24 RGB data bits are serialized along with three video control signals and up to two I2S data inputs.
EMI is minimized by the use of low voltage differential signaling, data scrambling and randomization and spread spectrum clocking compatibility.
The HDCP cipher engine is implemented in the serializer and deserializer. HDCP keys are stored in on-chip memory.
관심 가지실만한 유사 제품
다른 핀 출력을 지원하지만 비교 대상 장치와 동일한 기능.
기술 자료
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 |
|---|---|---|---|---|---|
| * | 데이터 시트 | DS90UH925Q-Q1 720p 24-bit Color FPD-Link III Serializer with HDCP datasheet (Rev. J) | PDF | HTML | 2014. 11. 7 | |
| 애플리케이션 노트 | Exploring the Int Test Pattern Generation Feature of FPD-Link III IVI Devices (Rev. G) | PDF | HTML | 2020. 11. 3 | ||
| 애플리케이션 노트 | Enabling GPIOs in DS90UB925 and DS90UB926 | 2015. 11. 10 | |||
| 애플리케이션 노트 | Using the I2S Audio Interface of DS90Ux92x FPD-Link III Devices | 2013. 5. 4 | |||
| 애플리케이션 노트 | I2C Communication Over FPD-Link III with Bidirectional Control Channel (Rev. A) | 2013. 4. 26 | |||
| 사용 설명서 | DS90UH925QSEVB User's Guide | 2012. 9. 20 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
DS90UH925QSEVB — DS90UH925QSEVB 평가 보드
The DS90UH925QSEVB is an evaluation board designed to demonstrate the performance and unique features of the DS90UH925Q FPD-Link III serializer.
The DS90UH925QSEVB board is designed to drive any of TI’s compatible FPD-Link III deserializer devices. The LVCMOS inputs of the DS90UH925Q are accessible (...)
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| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
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주문 및 품질
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