홈 인터페이스 이더넷 IC 이더넷 PHY
홈
인터페이스
이더넷 IC
이더넷 PHY

DP83TC818S-Q1

활성

MACsec, AVB 기능을 갖춘 고급 TSN, TC-10을 지원하는 오토모티브 100BASE-T1 이더넷 PHY

지금 주문하기
데이터 시트

DP83TC818S-Q1

활성
데이터 시트 지금 주문하기

제품 상세 정보

Datarate (Mbps) 100BASE-T1 Interface type MII, RGMII, RMII, SGMII Rating Automotive Number of ports Single Features 25-MHz clock out, Cable diagnostics, IEEE 1588v2/802.1AS time synchronization and AVB clock generation, IEEE 802.1AE MACsec, IEEE 802.3bw & Open Alliance (OA) compliant, Integrated LPF, Single supply, TC10, Wettable flank package I/O supply voltage (typ) (V) 1.8, 2.5, 3.3 Operating temperature range (°C) -40 to 125 Number of LEDs 2 ESD HBM (kV) 8
Datarate (Mbps) 100BASE-T1 Interface type MII, RGMII, RMII, SGMII Rating Automotive Number of ports Single Features 25-MHz clock out, Cable diagnostics, IEEE 1588v2/802.1AS time synchronization and AVB clock generation, IEEE 802.1AE MACsec, IEEE 802.3bw & Open Alliance (OA) compliant, Integrated LPF, Single supply, TC10, Wettable flank package I/O supply voltage (typ) (V) 1.8, 2.5, 3.3 Operating temperature range (°C) -40 to 125 Number of LEDs 2 ESD HBM (kV) 8
VQFN (RHA) 36 36 mm² (6 mm × 6 mm)
  • Synchronized Audio Clock Generation
    • I2S & TDMx SCLK/FSYNC clock generation
    • Configurable FSYNC, SCLK, MCLK frequencies
    • Automatic Phase Adjustment through IEEE1722 CRF decode
  • IEEE 802.1AE MACsec
    • MACsec frame expansion: Inbuilt buffering and flow control support to handle 12 byte IPG ethernet frames
    • Authentication, encryption at line rate
    • Cipher suites: GCM-AES-XPN-128/256, GCM-AES-128/256
    • Secure Channel: Total 16 SAK enabling 8 Tx/Rx SC with SAK Auto rollover support
    • Ingress/Egress classification for Ethertype, VLAN, DMAC: up to 8 parallel rules
    • Window replay protection
  • IEEE 802.1AS time synchronization
    • Highly accurate 1pps signal < ±15 ns
    • Precise time stamping for MACsec encoded PTP packets
    • Multiple IOs for event capture and trigger
  • Robust EMC Performance
    • IEC62228-5, OA EMC compliant
    • SAE J2962-3 EMC compliant
    • 39dBm DPI Immunity with ±5% assymetry
    • <4dBµV radiated emissions in GPS and Glonass bands
    • Stripline Emissions: Class-II compliant
  • TC-10 compliant
    • < 18µA sleep current
    • Fast wake from sleep by retaining PHY configuration during sleep (optional)
  • MAC Interfaces: MII, RMII Master, RGMII, SGMII
  • Footprint compatible with TI’s 1000BASE-T1 PHY
    • Single board design for 100BASE-T1 and 1000BASE-T1 with required BOM change
  • Diagnostic tool kit
    • Signal Quality Indication (SQI) & Time Domain Reflectometry (TDR)
    • Voltage, Temperature & ESD sensors
    • PPM monitor: Provides external clock ppm drift (up to ±100 ppb accuracy)
  • AEC-Q100 qualified for Automotive Applications:
    • Temperature Grade 1: –40°C to +125 °C
    • IEC61000-4-2 ESD level 4 MDI: ±8kV CD
  • Synchronized Audio Clock Generation
    • I2S & TDMx SCLK/FSYNC clock generation
    • Configurable FSYNC, SCLK, MCLK frequencies
    • Automatic Phase Adjustment through IEEE1722 CRF decode
  • IEEE 802.1AE MACsec
    • MACsec frame expansion: Inbuilt buffering and flow control support to handle 12 byte IPG ethernet frames
    • Authentication, encryption at line rate
    • Cipher suites: GCM-AES-XPN-128/256, GCM-AES-128/256
    • Secure Channel: Total 16 SAK enabling 8 Tx/Rx SC with SAK Auto rollover support
    • Ingress/Egress classification for Ethertype, VLAN, DMAC: up to 8 parallel rules
    • Window replay protection
  • IEEE 802.1AS time synchronization
    • Highly accurate 1pps signal < ±15 ns
    • Precise time stamping for MACsec encoded PTP packets
    • Multiple IOs for event capture and trigger
  • Robust EMC Performance
    • IEC62228-5, OA EMC compliant
    • SAE J2962-3 EMC compliant
    • 39dBm DPI Immunity with ±5% assymetry
    • <4dBµV radiated emissions in GPS and Glonass bands
    • Stripline Emissions: Class-II compliant
  • TC-10 compliant
    • < 18µA sleep current
    • Fast wake from sleep by retaining PHY configuration during sleep (optional)
  • MAC Interfaces: MII, RMII Master, RGMII, SGMII
  • Footprint compatible with TI’s 1000BASE-T1 PHY
    • Single board design for 100BASE-T1 and 1000BASE-T1 with required BOM change
  • Diagnostic tool kit
    • Signal Quality Indication (SQI) & Time Domain Reflectometry (TDR)
    • Voltage, Temperature & ESD sensors
    • PPM monitor: Provides external clock ppm drift (up to ±100 ppb accuracy)
  • AEC-Q100 qualified for Automotive Applications:
    • Temperature Grade 1: –40°C to +125 °C
    • IEC61000-4-2 ESD level 4 MDI: ±8kV CD

The DP83TC818S-Q1 is an IEEE 802.3bw and Open Alliance (OA) compliant automotive qualified 100Base-T1 Ethernet physical layer transceiver. The device provides all physical layer functions needed to transmit and receive data over unshielded/shielded single twisted-pair cables with xMII interface flexibility and TC10 Sleep-Wake functionality.

The DP83TC818S-Q1 integrates IEEE802.1AS / IEEE1588v2 hardware time stamping & fractional PLL, enabling highly accurate time synchronization. The fractional PLL enables frequency and phase synchronization of the wall clock (eliminating the need for external VCXO) and generation of a wide range of time synchronized frequencies needed for audio and other ADAS applications. The PHY also integrates IEEE 1722 CRF decode to generate Media clock and Bit Clock for AVB & other audio applications.

The DP83TC818S-Q1 integrates IEEE 802.1AE line rate security with authentication and optional encryption support to secure communication over the network. The DP83TC818S-Q1 supports up to 16 secure association (SA) channels with automatic SAK rollover and extended packet numbering support. DP83TC818S-Q1 offers ingress classification to filter the unwanted packets & supports WAN MACsec for end-to-end security.

The DP83TC818S-Q1 is footprint compatible to TI’s 100BASE-T1 PHYs and 1000BASE-T1 PHYs enabling design scalability with a single board for different speeds and features.

The DP83TC818S-Q1 is an IEEE 802.3bw and Open Alliance (OA) compliant automotive qualified 100Base-T1 Ethernet physical layer transceiver. The device provides all physical layer functions needed to transmit and receive data over unshielded/shielded single twisted-pair cables with xMII interface flexibility and TC10 Sleep-Wake functionality.

The DP83TC818S-Q1 integrates IEEE802.1AS / IEEE1588v2 hardware time stamping & fractional PLL, enabling highly accurate time synchronization. The fractional PLL enables frequency and phase synchronization of the wall clock (eliminating the need for external VCXO) and generation of a wide range of time synchronized frequencies needed for audio and other ADAS applications. The PHY also integrates IEEE 1722 CRF decode to generate Media clock and Bit Clock for AVB & other audio applications.

The DP83TC818S-Q1 integrates IEEE 802.1AE line rate security with authentication and optional encryption support to secure communication over the network. The DP83TC818S-Q1 supports up to 16 secure association (SA) channels with automatic SAK rollover and extended packet numbering support. DP83TC818S-Q1 offers ingress classification to filter the unwanted packets & supports WAN MACsec for end-to-end security.

The DP83TC818S-Q1 is footprint compatible to TI’s 100BASE-T1 PHYs and 1000BASE-T1 PHYs enabling design scalability with a single board for different speeds and features.
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추가 정보 요청

전체 데이터시트 및 추가 리소스가 제공됩니다. 지금 요청

기술 자료

검색된 결과가 없습니다. 검색어를 지우고 다시 시도하세요.
3개 모두 보기
상위 문서 유형 직함 형식 옵션 최신 영어 버전 다운로드 날짜
* 데이터 시트 DP83TC818S-Q1 Precise and Secure 100BASE-T1 Automotive Ethernet with AVB Clock Generation, IEEE802.1AE MACsec, IEEE802.1AS and TC10 Sleep-Wake datasheet (Rev. A) PDF | HTML 2024. 11. 19
백서 Time Sensitive Networking With Ethernet PHY PDF | HTML 2025. 1. 14
애플리케이션 노트 SGMII Troubleshooting Guide PDF | HTML 2024. 11. 5

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

평가 보드

DP83TC818EVM-MC — DP83TC818S-Q1 평가 모델

DP83TC818EVM-MC는 100Mbps 속도를 지원하며 IEEE 802.3bp와 호환됩니다. USB2MDIO 그래픽 사용자 인터페이스 도구와 함께 사용할 수 있는 온보드 MSP430F5529이 있습니다. DP83867은 RGMII MAC 인터페이스를 사용하는 구리(100BASE-TX) 지원을 위해 제공됩니다.

지원되는 제품 및 하드웨어
레퍼런스 디자인

TIDA-020071 — TDA4 쿼드 차량용 PHY RGMII 레퍼런스 설계

이 레퍼런스 설계는 RGMII 이더넷 확장 커넥터를 통해 Jacinto™ 7 프로세서 EVM 보드와 상호 작용합니다. 차량용 이더넷 연결은 TI의 차량용 이더넷 물리적 계층(PHY)을 통해 추가됩니다. 이 설계는 TI의 DP83TC818S-Q1 100Mbps 및 DP83TG721S-Q1 1000Mbps 단일 페어 이더넷(SPE) PHY의 구현을 보여줍니다.로 구현됩니다. 커플링 네트워크는 12V에서 데이터 라인에 결합하는 데 사용됩니다.

지원되는 제품 및 하드웨어
패키지 핀 CAD 기호, 풋프린트 및 3D 모델
VQFN (RHA) 36 Ultra Librarian
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주문 및 품질

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지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

포럼 주제 모두 보기(영문)

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