홈 마이크로컨트롤러(MCU) 및 프로세서 마이크로프로세서 및 DSP 오디오 및 레이더 DSP SoC
홈
마이크로컨트롤러(MCU) 및 프로세서
마이크로프로세서 및 DSP
오디오 및 레이더 DSP SoC

66AK2H14

활성

고성능 멀티코어 DSP+Arm - 4x Arm A15 코어, 8x C66x DSP 코어, 10GbE

지금 주문하기
데이터 시트
정오표

66AK2H14

활성
데이터 시트 지금 주문하기

제품 상세 정보

CPU 4 Arm Cortex-A15 Frequency (MHz) 1200, 1400 Coprocessors C66x DSP Protocols Ethernet PCIe 2 PCIe Gen 2 Hardware accelerators Packet Accelerator, Security Accelerator Features Networking Operating system Linux, RTOS Security Cryptographic acceleration, Device attestation & anti-counterfeit, Secure boot Rating Catalog Operating temperature range (°C) -40 to 100
CPU 4 Arm Cortex-A15 Frequency (MHz) 1200, 1400 Coprocessors C66x DSP Protocols Ethernet PCIe 2 PCIe Gen 2 Hardware accelerators Packet Accelerator, Security Accelerator Features Networking Operating system Linux, RTOS Security Cryptographic acceleration, Device attestation & anti-counterfeit, Secure boot Rating Catalog Operating temperature range (°C) -40 to 100
FCBGA (AAW) 1517 1600 mm² 40 x 40
  • Eight TMS320C66x DSP Core Subsystems (C66x CorePacs), Each With
    • 1.0 GHz or 1.2 GHz C66x Fixed- and Floating-Point DSP Core
      • 38.4 GMacs/Core for Fixed Point @ 1.2 GHz
      • 19.2 GFlops/Core for Floating Point @ 1.2 GHz
    • Memory
      • 32-KB L1P Per CorePac
      • 32-KB L1D Per CorePac
      • 1024-KB Local L2 Per CorePac
  • ARM CorePac
    • Four ARM® Cortex®-A15 MPCore™ Processors at up to 1.4 GHz
    • 4MB of L2 Cache Memory Shared by Four ARM Cores
    • Full Implementation of ARMv7-A Architecture Instruction Set
    • 32-KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE) Master Port, Connected to MSMC for Low-Latency Access to Shared MSMC SRAM
  • Multicore Shared Memory Controller (MSMC)
    • 6MB of MSM SRAM Memory Shared by Eight DSP CorePacs and One ARM CorePac
    • Memory Protection Unit (MPU) for Both MSM SRAM and DDR3_EMIF
  • Multicore Navigator
    • 16k Multipurpose Hardware Queues With Queue Manager
    • Packet-Based DMA for Zero-Overhead Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • Transport Plane IPsec, GTP-U, SCTP, PDCP
      • L2 User Plane PDCP (RoHC, Air Ciphering)
      • 1-Gbps Wire Speed Throughput at 1.5 MPackets Per Second
    • Security Accelerator Engine Enables Support for
      • IPSec, SRTP, 3GPP, and WiMAX Air Interface, and SSL/TLS Security
      • ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC, CMAC, GMAC, AES, DES, 3DES, Kasumi, SNOW 3G, SHA-1, SHA-2 (256-Bit Hash), MD5
      • Up to 2.4 Gbps IPSec and 2.4 Gbps Air Ciphering
    • Ethernet Subsystem
      • Five-Port Switch (Four SGMII Ports)
  • Peripherals
    • Four Lanes of SRIO 2.1
      • Supports up to 5 GBaud
      • Supports Direct I/O, Message Passing
    • Two Lanes PCIe Gen2
      • Supports up to 5 GBaud
    • Two HyperLinks
      • Supports Connections to Other KeyStone™ Architecture Devices Providing Resource Scalability
      • Supports up to 50 GBaud
    • 10-Gigabit Ethernet (10-GbE) Switch Subsystem (66AK2H14 Only)
      • Two XFI Ports
      • IEEE 1588 Support
    • Five Enhanced Direct Memory Access (EDMA) Modules
    • Two 72-Bit DDR3/DDR3L Interfaces With Speeds up to 1600 MHz
    • EMIF16 Interface
    • USB 3.0
    • Two UART Interfaces
    • Three I2C Interfaces
    • 32 GPIO Pins
    • Three SPI Interfaces
    • Semaphore Module
    • 64-Bit Timers
      • Twenty 64-Bit Timers for 66AK2H14 and 66AK2H12
      • Fourteen 64-Bit Timers for 66AK2H06
    • Five On-Chip PLLs
  • Commercial Case Temperature:
    • 0ºC to 85ºC
  • Extended Case Temperature:
    • –40ºC to 100ºC
  • Eight TMS320C66x DSP Core Subsystems (C66x CorePacs), Each With
    • 1.0 GHz or 1.2 GHz C66x Fixed- and Floating-Point DSP Core
      • 38.4 GMacs/Core for Fixed Point @ 1.2 GHz
      • 19.2 GFlops/Core for Floating Point @ 1.2 GHz
    • Memory
      • 32-KB L1P Per CorePac
      • 32-KB L1D Per CorePac
      • 1024-KB Local L2 Per CorePac
  • ARM CorePac
    • Four ARM® Cortex®-A15 MPCore™ Processors at up to 1.4 GHz
    • 4MB of L2 Cache Memory Shared by Four ARM Cores
    • Full Implementation of ARMv7-A Architecture Instruction Set
    • 32-KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE) Master Port, Connected to MSMC for Low-Latency Access to Shared MSMC SRAM
  • Multicore Shared Memory Controller (MSMC)
    • 6MB of MSM SRAM Memory Shared by Eight DSP CorePacs and One ARM CorePac
    • Memory Protection Unit (MPU) for Both MSM SRAM and DDR3_EMIF
  • Multicore Navigator
    • 16k Multipurpose Hardware Queues With Queue Manager
    • Packet-Based DMA for Zero-Overhead Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • Transport Plane IPsec, GTP-U, SCTP, PDCP
      • L2 User Plane PDCP (RoHC, Air Ciphering)
      • 1-Gbps Wire Speed Throughput at 1.5 MPackets Per Second
    • Security Accelerator Engine Enables Support for
      • IPSec, SRTP, 3GPP, and WiMAX Air Interface, and SSL/TLS Security
      • ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC, CMAC, GMAC, AES, DES, 3DES, Kasumi, SNOW 3G, SHA-1, SHA-2 (256-Bit Hash), MD5
      • Up to 2.4 Gbps IPSec and 2.4 Gbps Air Ciphering
    • Ethernet Subsystem
      • Five-Port Switch (Four SGMII Ports)
  • Peripherals
    • Four Lanes of SRIO 2.1
      • Supports up to 5 GBaud
      • Supports Direct I/O, Message Passing
    • Two Lanes PCIe Gen2
      • Supports up to 5 GBaud
    • Two HyperLinks
      • Supports Connections to Other KeyStone™ Architecture Devices Providing Resource Scalability
      • Supports up to 50 GBaud
    • 10-Gigabit Ethernet (10-GbE) Switch Subsystem (66AK2H14 Only)
      • Two XFI Ports
      • IEEE 1588 Support
    • Five Enhanced Direct Memory Access (EDMA) Modules
    • Two 72-Bit DDR3/DDR3L Interfaces With Speeds up to 1600 MHz
    • EMIF16 Interface
    • USB 3.0
    • Two UART Interfaces
    • Three I2C Interfaces
    • 32 GPIO Pins
    • Three SPI Interfaces
    • Semaphore Module
    • 64-Bit Timers
      • Twenty 64-Bit Timers for 66AK2H14 and 66AK2H12
      • Fourteen 64-Bit Timers for 66AK2H06
    • Five On-Chip PLLs
  • Commercial Case Temperature:
    • 0ºC to 85ºC
  • Extended Case Temperature:
    • –40ºC to 100ºC

The 66AK2Hxx platform combines the quad ARM Cortex-A15 processor with up to eight TMS320C66x high-performance DSPs using the KeyStone II architecture. The 66AK2H14/12/06 device provides up to 5.6 GHz of ARM and 9.6 GHz of DSP processing coupled with security, packet processing, and Ethernet switching at lower power than multichip solutions. The 66AK2H14/12/06 device is optimal for embedded infrastructure applications like cloud computing, media processing, high-performance computing, transcoding, security, gaming, analytics, and virtual desktop.

The C66x core combines fixed-point and floating-point computational capability in the processor without sacrificing speed, size, or power consumption. The raw computational performance is 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz operating frequency). The C66x is also 100% backward compatible with software for C64x+ devices. The C66x core incorporates 90 new instructions targeted for floating point (FPi) and vector math oriented (VPi) processing.

The 66AK2H14/12/06 device has a complete set of development tools that includes: a C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

The 66AK2Hxx platform combines the quad ARM Cortex-A15 processor with up to eight TMS320C66x high-performance DSPs using the KeyStone II architecture. The 66AK2H14/12/06 device provides up to 5.6 GHz of ARM and 9.6 GHz of DSP processing coupled with security, packet processing, and Ethernet switching at lower power than multichip solutions. The 66AK2H14/12/06 device is optimal for embedded infrastructure applications like cloud computing, media processing, high-performance computing, transcoding, security, gaming, analytics, and virtual desktop.

The C66x core combines fixed-point and floating-point computational capability in the processor without sacrificing speed, size, or power consumption. The raw computational performance is 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz operating frequency). The C66x is also 100% backward compatible with software for C64x+ devices. The C66x core incorporates 90 new instructions targeted for floating point (FPi) and vector math oriented (VPi) processing.

The 66AK2H14/12/06 device has a complete set of development tools that includes: a C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

filter 기타 오디오 및 레이더 DSP SoC 찾기
다운로드 스크립트와 함께 비디오 보기 비디오

기술 자료

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82개 모두 보기
상위 문서 유형 직함 형식 옵션 날짜
* Data sheet 66AK2Hxx Multicore DSP+ARM® KeyStone II System-on-Chip (SoC) datasheet (Rev. G) PDF | HTML 2017/10/09
* Errata 66AK2Hxx Multicore DSP+ARM KeyStone II SOC Errata (Revs 1.0, 1.1, 2.0, 3.0, 3.1) (Rev. F) 2018/06/05
Application note Introduction to HVDC Architecture and Solutions for Control and Protection (Rev. C) PDF | HTML 2026/05/19
User guide ARM Assembly Language Tools v20.2.0.LTS User's Guide (Rev. Z) PDF | HTML 2023/03/30
User guide ARM Optimizing C/C++ Compiler v20.2.0.LTS User's Guide (Rev. W) PDF | HTML 2023/03/30
Application note DDR3 Design Requirements for KeyStone Devices (Rev. D) PDF | HTML 2022/07/07
Application note Keystone Error Detection and Correction EDC ECC (Rev. A) 2021/06/25
Application note How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A) PDF | HTML 2021/05/19
Application note Implementing an FTP Server on TI 66AK2H Device With RTOS PDF | HTML 2020/08/17
Application note Using DSPLIB FFT Implementation for Real Input and Without Data Scaling PDF | HTML 2019/06/11
Application note Using Arm ROM Bootloader on Keystone II Devices PDF | HTML 2019/06/04
User guide ARM Assembly Language Tools v19.6.0.STS User's Guide (Rev. X) 2019/06/03
User guide ARM Optimizing C/C++ Compiler v19.6.0.STS User's Guide (Rev. U) 2019/06/03
Application note Keystone Multicore Device Family Schematic Checklist PDF | HTML 2019/05/17
Application note KeyStone II DDR3 interface bring-up 2019/03/07
User guide ARM Assembly Language Tools v18.12.0.LTS User's Guide (Rev. W) 2018/11/19
User guide ARM Optimizing C/C++ Compiler v18.12.0.LTS User's Guide (Rev. T) 2018/11/19
White paper Designing professional audio mixers for every scenario 2018/06/28
User guide ARM Assembly Language Tools v18.1.0.LTS User's Guide (Rev. U) 2018/01/16
User guide ARM Optimizing C/C++ Compiler v18.1.0.LTS User's Guide (Rev. R) 2018/01/16
User guide ARM Assembly Language Tools v17.9.0.STS User's Guide (Rev. T) 2017/09/30
User guide ARM Optimizing C/C++ Compiler v17.9.0.STS User's Guide (Rev. Q) 2017/09/30
User guide KeyStone II Architecture Universal Serial Bus 3.0 (USB 3.0) (Rev. A) 2017/08/21
Application note Thermal Design Guide for DSP and Arm Application Processors (Rev. B) 2017/08/14
User guide Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I) 2017/07/26
User guide ARM Assembly Language Tools v17.6.0.STS User's Guide (Rev. S) 2017/06/21
User guide ARM Optimizing C/C++ Compiler v17.6.0.STS User's Guide (Rev. P) 2017/06/21
Application note PCI Express (PCIe) Resource Wiki for Keystone Devices (Rev. A) 2017/05/19
User guide Serializer/Deserializer (SerDes) for KeyStone II Devices User Guide (Rev. A) 2016/07/27
Application note Power Management of KS2 Device (Rev. C) 2016/07/15
User guide ARM Assembly Language Tools v16.9.0.LTS User's Guide (Rev. P) 2016/04/30
User guide ARM Optimizing C/C++ Compiler v16.9.0.LTS User's Guide (Rev. M) 2016/04/30
Application note SERDES Link Commissioning on KeyStone I and II Devices 2016/04/13
White paper Multicore SoCs stay a step ahead of SoC FPGAs 2016/02/23
Application note TI DSP Benchmarking 2016/01/13
Application note Throughput Performance Guide for KeyStone II Devices (Rev. B) 2015/12/22
Application note Keystone II DDR3 Debug Guide 2015/10/16
User guide Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B) 2015/05/06
User guide Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H) PDF | HTML 2015/04/09
User guide DDR3 Memory Controller for KeyStone II Devices User's Guide (Rev. C) 2015/03/27
White paper TI’s processors leading the way in embedded analytics 2015/03/03
Application note Keystone II DDR3 Initialization 2015/01/26
User guide ARM Assembly Language Tools v5.2 User's Guide (Rev. M) 2014/11/05
User guide ARM Optimizing C/C++ Compiler v5.2 User's Guide (Rev. J) 2014/11/05
User guide Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C) 2014/09/04
User guide Serial RapidIO (SRIO) for KeyStone Devices User's Guide (Rev. C) 2014/09/03
White paper KeyStone™-II-based processors: 10G Ethernet as an optical interface 2014/08/25
Application note Hardware Design Guide for KeyStone II Devices 2014/03/24
Product overview The Case for 10G Ethernet in Embedded Processing 2013/11/13
Product overview 66AK2Hx KeyStone Multicore DSP+ARM System-on-chips (Rev. A) 2013/11/08
User guide PCI Express (PCIe) for KeyStone Devices User's Guide (Rev. D) 2013/09/30
User guide Debug and Trace for KeyStone II Devices User's Guide 2013/07/26
User guide ARM Bootloader User Guide for KeyStone II Devices 2013/07/21
User guide DSP Bootloader for KeyStone Architecture User's Guide (Rev. C) 2013/07/15
User guide Gigabit Ethernet Switch Subsystem for KeyStone Devices User's Guide (Rev. D) 2013/07/03
User guide C66x CorePac User's Guide (Rev. C) 2013/06/28
User guide Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A) 2013/06/28
User guide HyperLink for KeyStone Devices User's Guide (Rev. C) 2013/05/28
User guide 10 Gigabit Ethernet Switch Subsystem User Guide for KeyStone II Devices 2013/02/08
User guide Security Accelerator (SA) for KeyStone Devices User's Guide (Rev. B) 2013/02/05
Product overview Multicore DSPs for High-Performance Video Coding 2013/01/22
User guide Multicore Shared Memory Controller (MSMC) User Guide for KeyStone II Devices 2012/11/12
Product overview Industrial Imaging: Applications of the K2H and K2E platforms 2012/11/09
Product overview Video Infrastructure - Applications of the K2E, K2H platforms 2012/11/09
User guide ARM CorePac User Guide for KeyStone II Devices 2012/10/31
Application note Multicore Programming Guide (Rev. B) 2012/08/29
User guide Packet Accelerator (PA) for KeyStone Devices User's Guide (Rev. A) 2012/07/11
User guide Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A) 2012/03/30
User guide Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A) 2012/03/27
User guide 64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A) 2012/03/22
Application note PCIe Use Cases for KeyStone Devices 2011/12/13
Application note Introduction to TMS320C6000 DSP Optimization 2011/10/06
User guide Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide 2011/09/02
User guide External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A) 2011/05/24
White paper Software and Hardware Design Challenges Due to Dynamic Raw NAND Market 2011/05/19
User guide C66x CPU and Instruction Set Reference Guide 2010/11/09
User guide C66x DSP Cache User's Guide 2010/11/09
Application note Clocking Design Guide for KeyStone Devices 2010/11/09
User guide General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide 2010/11/09
Application note Optimizing Loops on the C66x DSP 2010/11/09
User guide Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices UG 2010/11/09
User guide Network Coprocessor for KeyStone Devices User's Guide 2010/11/02

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TMDSEMU200-U — XDS200 USB 디버그 프로브

XDS200은 TI 임베디드 장치를 디버깅하는 데 사용되는 디버그 프로브(에뮬레이터)입니다. 대부분의 장치의 경우 더욱 저렴한 신형 XDS110(www.ti.com/tool/TMDSEMU110-U)을 사용하실 것을 권장합니다. XDS200은 단일 포드에서 다양한 표준(IEEE1149.1, IEEE1149.7, SWD)을 지원합니다. 모든 XDS 디버그 프로브는 ETB(임베디드 트레이스 버퍼)가 포함되어 있는 모든 Arm® 및 DSP 프로세서에서 코어 및 시스템 트레이스를 지원합니다.

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XDS560v2는 디버그 프로브의 XDS560™ 제품군 중 최고의 성능을 가진 제품으로, 기존의 JTAG 표준(IEEE1149.1)과 cJTAG(IEEE1149.7)를 모두 지원합니다. SWD(직렬 와이어 디버그)는 지원하지 않습니다.

모든 XDS 디버그 프로브는 ETB(Embedded Trace Buffer)를 특징으로 하는 모든 ARM 및 DSP 프로세서에서 코어 및 시스템 추적을 지원합니다. 핀을 통한 추적의 경우 XDS560v2 PRO TRACE가 필요합니다.

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All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

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소프트웨어 개발 키트(SDK)

BIOSLINUXMCSDK-K2 — MCSDK supporting SYS/BIOS RTOS and Linux OS for KeyStone II ARM A15 + DSP C66x

NOTE: K2x, C665x and C667x devices are now actively maintained on the Processor-SDK release stream. See links above.

Our Multicore Software Development Kits (MCSDK) provide highly-optimized bundles of foundational, platform-specific drivers to enable development on selected TI ARM and DSP devices. (...)

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PROCESSOR-SDK-LINUX-K2HK — Linux Processor SDK for K2H

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PROCESSOR-SDK-LINUX-RT-K2HK — Linux-RT Processor SDK for K2H

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드라이버 또는 라이브러리

SPRC265 — TMS320C6000 DSP 라이브러리(DSPLIB)

TMS320C6000 DSPLIB(디지털 신호 프로세서 라이브러리)는 C 프로그래머를 위한 플랫폼에 최적화된 DSP 기능 라이브러리입니다. 여기에는 일반적으로 계산 집약적 실시간 애플리케이션에서 사용되는 C 호출 가능한 범용 신호 처리 루틴이 포함되어 있습니다. 이 루틴을 사용하면 상응하는 표준 ANSI C 언어 코드보다 더 높은 성능을 달성할 수 있습니다. DSPLIB는 즉시 사용할 수 있는 DSP 기능을 소스 코드와 함께 제공하여 애플리케이션 개발 시간을 크게 단축시킬 수 있습니다.


벤치마크 확인: DSP 코어 벤치마크

사용 설명서: PDF
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IDE, 구성, 컴파일러 또는 디버거

CCSTUDIO — Code Composer Studio integrated development environment (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어
시작 다운로드 옵션
소프트웨어 코덱

C66XCODECS — 코덱 - 비디오, 음성 - C66x 기반 디바이스

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into video and voice applications. In many cases, the C64x+ codecs are provided and validated for C66x platforms. Datasheets and Release Notes are on the download (...)
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시뮬레이션 모델

66AK2H14 AAW BSDL Model

SPRM608.ZIP (36 KB) - BSDL Model
다운로드
시뮬레이션 모델

66AK2H14 AAW IBIS Model

SPRM619.ZIP (2189 KB) - IBIS Model
다운로드
시뮬레이션 모델

66AK2H14 Power Consumption Model (Rev. A)

SPRM651A.ZIP (135 KB) - Power Model
다운로드
시뮬레이션 모델

66AK2Hx FloTherm Model

SPRM603.ZIP (6 KB) - Power Model
다운로드
시뮬레이션 모델

KeyStone II IBIS AMI Models

SPRM743.ZIP (265889 KB) - IBIS-AMI Model
lock = 수출 승인 필요(1분)
lock 다운로드
회로도

66AK2H14 66AK2H12 66AK2H106 AAW OrCAD Symbols

SPRR189.ZIP (144 KB)
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레퍼런스 디자인

TIDEP0045 — TI의 C6678 DSP에서 실시간 SAR(합성 개구면 레이더) 구현 레퍼런스 디자인

이 레퍼런스 설계는 멀티코어 TMS320C6678 디지털 신호 프로세서(DSP)에서 실행되는 실시간 합성 개구면 레이더(SAR)를 보여줍니다. SAR의 주요 과제 중 하나는 실시간으로 고해상도 이미지를 생성하는 것입니다. 이미지를 형성하는 데는 계산적으로 까다로운 신호 처리 절차가 필요하기 때문입니다.   전체 애플리케이션 성능과 1개, 2개, 4개, 8개 DSP 코어에 걸쳐 어떻게 확장되는지 보여주기 위해 C6678 8코어 고정 소수점 및 부동 소수점 DSP에 SAR 알고리즘을 구현했습니다. 여기서 범위 도플러 SAR 처리 (...)
Design guide: PDF
회로도: PDF
레퍼런스 디자인

TIDEP0037 — TMS320C6678 프로세서를 사용하여 전력 효율 확장 가능한 H.265/HEVC 솔루션 구현 레퍼런스 디자인

HEVC is an efficient, but processing intensive video standard, that is said to double the data compression ratio compared to H.264 / MPEG-4 at the same level of video quality. This design shows how a power efficient, soft H.265 / HEVC solution, that scales across resolutions, frame rates & (...)
Design guide: PDF
회로도: PDF
패키지 핀 CAD 기호, 풋프린트 및 3D 모델
FCBGA (AAW) 1517 Ultra Librarian
TI의 평가 항목에 대한 표준 약관이 적용됩니다.

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

포럼 주제 모두 보기(영문)

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