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TMS320C6211B

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C62x-Festkomma-DSP – bis zu 167 MHz

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TMS320C6211B

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Produktdetails

CPU 32-/64-bit Frequency (MHz) 167 Rating Catalog Operating temperature range (°C) -40 to 105
CPU 32-/64-bit Frequency (MHz) 167 Rating Catalog Operating temperature range (°C) -40 to 105
BGA (ZFN) 256 729 mm² (27 mm × 27 mm) PBGA (GFN) 256 729 mm² (27 mm × 27 mm)
  • Excellent Price/Performance Digital Signal Processors (DSPs): TMS320C62x™ (TMS320C6211 and TMS320C6211B)
    • Eight 32-Bit Instructions/Cycle
    • C6211, C6211B, C6711, and C6711B are Pin-Compatible
    • 150-, 167-MHz Clock Rates
    • 6.7-, 6-ns Instruction Cycle Time
    • 1200, 1333 MIPS
    • Extended Temperature Device (C6211B)
  • VelociTI™ Advanced Very Long Instruction Word (VLIW) C62x™ DSP Core (C6211/11B)
    • Eight Highly Independent Functional Units:
      • Six ALUs (32-/40-Bit)
      • Two 16-Bit Multipliers (32-Bit Results)
    • Load-Store Architecture With 32 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-, 16-, 32-Bit Data)
    • 8-Bit Overflow Protection
    • Saturation
    • Bit-Field Extract, Set, Clear
    • Bit-Counting
    • Normalization
  • L1/L2 Memory Architecture
    • 32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped)
    • 32K-Bit (4K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation)
  • Device Configuration
    • Boot Mode: HPI, 8-, 16-, and 32-Bit ROM Boot
    • Endianness: Little Endian, Big Endian
  • 32-Bit External Memory Interface (EMIF)
    • Glueless Interface to Asynchronous Memories: SRAM and EPROM
    • Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
    • 512M-Byte Total Addressable External Memory Space
  • Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)
  • 16-Bit Host-Port Interface (HPI)
    • Access to Entire Memory Map
  • Two Multichannel Buffered Serial Ports (McBSPs)
    • Direct Interface to T1/E1, MVIP, SCSA Framers
    • ST-Bus-Switching Compatible
    • Up to 256 Channels Each
    • AC97-Compatible
    • Serial-Peripheral-Interface (SPI) Compatible (Motorola™)
  • Two 32-Bit General-Purpose Timers
  • Flexible Phase-Locked-Loop (PLL) Clock Generator
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • 256-Pin Ball Grid Array (BGA) Package (GFN and ZFN Suffixes)
  • 0.18-µm/5-Level Metal Process
    • CMOS Technology
  • 3.3-V I/Os, 1.8-V Internal

TMS320C62x, VelociTI, and C62x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
All trademarks are the property of their respective owners.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
  • Excellent Price/Performance Digital Signal Processors (DSPs): TMS320C62x™ (TMS320C6211 and TMS320C6211B)
    • Eight 32-Bit Instructions/Cycle
    • C6211, C6211B, C6711, and C6711B are Pin-Compatible
    • 150-, 167-MHz Clock Rates
    • 6.7-, 6-ns Instruction Cycle Time
    • 1200, 1333 MIPS
    • Extended Temperature Device (C6211B)
  • VelociTI™ Advanced Very Long Instruction Word (VLIW) C62x™ DSP Core (C6211/11B)
    • Eight Highly Independent Functional Units:
      • Six ALUs (32-/40-Bit)
      • Two 16-Bit Multipliers (32-Bit Results)
    • Load-Store Architecture With 32 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-, 16-, 32-Bit Data)
    • 8-Bit Overflow Protection
    • Saturation
    • Bit-Field Extract, Set, Clear
    • Bit-Counting
    • Normalization
  • L1/L2 Memory Architecture
    • 32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped)
    • 32K-Bit (4K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation)
  • Device Configuration
    • Boot Mode: HPI, 8-, 16-, and 32-Bit ROM Boot
    • Endianness: Little Endian, Big Endian
  • 32-Bit External Memory Interface (EMIF)
    • Glueless Interface to Asynchronous Memories: SRAM and EPROM
    • Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
    • 512M-Byte Total Addressable External Memory Space
  • Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)
  • 16-Bit Host-Port Interface (HPI)
    • Access to Entire Memory Map
  • Two Multichannel Buffered Serial Ports (McBSPs)
    • Direct Interface to T1/E1, MVIP, SCSA Framers
    • ST-Bus-Switching Compatible
    • Up to 256 Channels Each
    • AC97-Compatible
    • Serial-Peripheral-Interface (SPI) Compatible (Motorola™)
  • Two 32-Bit General-Purpose Timers
  • Flexible Phase-Locked-Loop (PLL) Clock Generator
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • 256-Pin Ball Grid Array (BGA) Package (GFN and ZFN Suffixes)
  • 0.18-µm/5-Level Metal Process
    • CMOS Technology
  • 3.3-V I/Os, 1.8-V Internal

TMS320C62x, VelociTI, and C62x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
All trademarks are the property of their respective owners.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

The TMS320C62x™ DSPs (including the TMS320C6211/C6211B devices) compose one of the fixed-point DSP families in the TMS320C6000™ DSP platform. The TMS320C6211 (C6211) and TMS320C6211B (C6211B) devices are based on the high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications.

With performance of up to 1333 million instructions per second (MIPS) at a clock rate of 167 MHz, the C6211/C6211B device offers cost-effective solutions to high-performance DSP programming challenges. The C6211/C6211B DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6211/C6211B can produce two multiply-accumulates (MACs) per cycle for a total of 333 million MACs per second (MMACS). The C6211/C6211B DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The C6211/C6211B uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 512-Kbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM and asynchronous peripherals.

The C6211/C6211B has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

The TMS320C62x™ DSPs (including the TMS320C6211/C6211B devices) compose one of the fixed-point DSP families in the TMS320C6000™ DSP platform. The TMS320C6211 (C6211) and TMS320C6211B (C6211B) devices are based on the high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications.

With performance of up to 1333 million instructions per second (MIPS) at a clock rate of 167 MHz, the C6211/C6211B device offers cost-effective solutions to high-performance DSP programming challenges. The C6211/C6211B DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6211/C6211B can produce two multiply-accumulates (MACs) per cycle for a total of 333 million MACs per second (MMACS). The C6211/C6211B DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The C6211/C6211B uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 512-Kbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM and asynchronous peripherals.

The C6211/C6211B has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.
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Technische Dokumentation

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Top-Dokumentation Typ Titel Format-Optionen Neueste englische Version herunterladen Datum
* Datenblatt TMS320C6211, TMS320C6211B Fixed-Point Digital Signal Processors datasheet (Rev. L) 09.06.2004
* Errata TMS320C6211/TMS320C6211B DSPs Silicon Errata (Revs 1.0, 1.1, 2.1, 2.2, 3.0, 3.1) (Rev. L) 28.05.2004
Anwendungshinweis How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A) PDF | HTML 19.05.2021
Anwendungshinweis Introduction to TMS320C6000 DSP Optimization 06.10.2011
Benutzerhandbuch TMS320C62x DSP CPU and Instruction Set Reference Guide (Rev. A) 20.05.2010
Benutzerhandbuch TMS320C6000 DSP Peripherals Overview Reference Guide (Rev. Q) 02.07.2009
Anwendungshinweis TMS320C6000 EMIF-to-External SDRAM Interface (Rev. E) 04.09.2007
Anwendungshinweis Thermal Considerations for the DM64xx, DM64x, and C6000 Devices 20.05.2007
Benutzerhandbuch TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide (Rev. E) 11.04.2007
Benutzerhandbuch TMS320C6000 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (Rev. G) 14.12.2006
Benutzerhandbuch TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (Rev. C) 15.11.2006
Benutzerhandbuch TMS320C6000 CPU and Instruction Set Reference Guide (Rev. G) 11.07.2006
Benutzerhandbuch TMS320C6000 DSP Host-Post Interface (HPI) Reference Guide (Rev. C) 01.01.2006
Anwendungshinweis Migrating from TMS320C6211B/C6711/C6711B and C6713 to TMS320C6713B (Rev. H) 11.11.2005
Anwendungshinweis Migrating From TMS320C6211B/C6711/C6711B/C6711C to TMS320C6711D (Rev. H) 10.11.2005
Benutzerhandbuch TMS320C6000 DSP Power-Down Logic and Modes Reference Guide (Rev. C) 01.03.2005
Benutzerhandbuch TMS320C6000 DSP 32-bit Timer Reference Guide (Rev. B) 25.01.2005
Benutzerhandbuch TMS320C621x/C671x DSP Two Level Internal Memory Reference Guide (Rev. B) 08.06.2004
Anwendungshinweis TMS320C6000 Tools: Vector Table and Boot ROM Creation (Rev. D) 26.04.2004
Anwendungshinweis TMS320C6000 Board Design: Considerations for Debug (Rev. C) 21.04.2004
Anwendungshinweis TMS320C6000 McBSP Initialization (Rev. C) 08.03.2004
Anwendungshinweis TMS320C621x/TMS320C671x EDMA Architecture 05.03.2004
Anwendungshinweis TMS320C621x/671x EDMA Performance Data 05.03.2004
Benutzerhandbuch TMS320C6000 DSP Designing for JTAG Emulation Reference Guide 31.07.2003
Benutzerhandbuch TMS320C6000 DSP Cache User's Guide (Rev. A) 05.05.2003
Anwendungshinweis Migrating from TMS320C6211 to TMS320C6211B 28.04.2003
Anwendungshinweis Using IBIS Models for Timing Analysis (Rev. A) 15.04.2003
Anwendungshinweis Extended Precision Radix-4 Fast Fourier Transform Implemented on the TMS320C62x 23.11.2002
Anwendungshinweis TMS320C6000 McBSP Interface to an ST-BUS Device (Rev. B) 04.06.2002
Anwendungshinweis TMS320C6000 HPI to PCI Interfacing Using the PLX PCI9050 (Rev. C) 17.04.2002
Anwendungshinweis TMS320C6000 DMA Example Applications (Rev. A) 10.04.2002
Anwendungshinweis TMS320C6000 Board Design for JTAG (Rev. C) 02.04.2002
Anwendungshinweis TMS320C6000 EMIF to External Flash Memory (Rev. A) 13.02.2002
Anwendungshinweis Using a TMS320C6000 McBSP for Data Packing (Rev. A) 31.10.2001
Anwendungshinweis TMS320C6000 Enhanced DMA: Example Applications (Rev. A) 24.10.2001
Anwendungshinweis Interfacing theTMS320C6000 EMIFto a PCI Bus Using the AMCC S5933 PCI Controller (Rev. A) 30.09.2001
Anwendungshinweis TMS320C6000 Host Port to MC68360 Interface (Rev. A) 30.09.2001
Anwendungshinweis Using the TMS320C6000 McBSP as a High Speed Communication Port (Rev. A) 31.08.2001
Anwendungshinweis TMS320C6000 Host Port to the i80960 Microprocessors Interface (Rev. A) 31.08.2001
Anwendungshinweis TMS320C6000 EMIF to External Asynchronous SRAM Interface (Rev. A) 31.08.2001
Anwendungshinweis TMS320C6000 System Clock Circuit Example (Rev. A) 15.08.2001
Anwendungshinweis TMS320C6000 McBSP to Voice Band Audio Processor (VBAP) Interface (Rev. A) 23.07.2001
Anwendungshinweis TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27) (Rev. A) 10.07.2001
Anwendungshinweis TMS320C6000 McBSP: Interface to SPI ROM (Rev. C) 30.06.2001
Anwendungshinweis TMS320C6000 Host Port to MPC860 Interface (Rev. A) 21.06.2001
Anwendungshinweis TMS320C6000 McBSP: IOM-2 Interface (Rev. A) 21.05.2001
Anwendungshinweis ETSI Math Operations in C for the TMS320C62x (Rev. A) 13.11.2000
Anwendungshinweis TMS320C621x/C671x EDMA Queue Management Guidelines 07.11.2000
Anwendungshinweis Optimizing JPEG on the TMS320C6211 2-Level Cache DSP 13.09.2000
Anwendungshinweis Circular Buffering on TMS320C6000 (Rev. A) 12.09.2000
Anwendungshinweis TMS320C6000 McBSP as a TDM Highway (Rev. A) 11.09.2000
Anwendungshinweis MPEG-2 Video Decoder: TMS320C62x (TM) DSP Implementation 29.02.2000
Anwendungshinweis TMS320C6000 u-Law and a-Law Companding with Software or the McBSP 02.02.2000
Anwendungshinweis General Guide to Implement Logarithmic and Exponential Operations on Fixed-Point 31.01.2000
Anwendungshinweis G.723.1 Dual Rate Speech Coder: Multichannel TMS320C62x Implementation (Rev. B) 04.01.2000
Anwendungshinweis GSM Enhanced Full Rate Speech Coder: Multichannel TMS320C62x Implementation (Rev. B) 04.01.2000
Anwendungshinweis IS-127 Enhanced Var Rate Speech Coder:Multichannel TMS320C62x Implementation (Rev. B) 04.01.2000
Anwendungshinweis G.729/A Speech Coder: Multichannel TMS320C62x Implementation (Rev. B) 04.01.2000
Anwendungshinweis TMS320C6000 C Compiler: C Implementation of Intrinsics 07.12.1999
Anwendungshinweis TMS320C6000 McBSP: I2S Interface 08.09.1999
Anwendungshinweis On the Implementation of MPEG-4 Motion Compensation Using the TMS320C62x 29.07.1999

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