SN74LVC2G79

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Zweifach-Flipflop, Typ D, mit positiver Flankensteuerung

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Datenblatt

document-pdfAcrobat Dual Positive-Edge-Triggered D-Type Flip-Flop, SN74LVC2G79 datasheet (Rev. E) (Englisch)

SN74LVC2G79

AKTIV

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Produktdetails

Number of channels

2

Technology family

LVC

Input type

Standard CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

150

IOL (max) (mA)

32

IOH (max) (mA)

-32

Supply current (max) (µA)

5

Features

Balanced outputs

Operating temperature range (°C)

-40 to 125

Rating

Catalog

Number of channels

2

Technology family

LVC

Input type

Standard CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

150

IOL (max) (mA)

32

IOH (max) (mA)

-32

Supply current (max) (µA)

5

Features

Balanced outputs

Operating temperature range (°C)

-40 to 125

Rating

Catalog

DSBGA (YZP)

8

2.8125 mm² (— mm × — mm)

SSOP (DCT)

8

11.8 mm² (2.95 mm × 4 mm)

VSSOP (DCU)

8

6.2 mm² (2 mm × 3.1 mm)

Available in the Texas Instruments NanoFree Package
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Max t_pd of 4.2 ns at 3.3 V
Low Power Consumption, 10-μA Max I_CC
±24-mA Output Drive at 3.3 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
I_off Feature Supports Live Insertion, Partial-Power-Down Mode Operation and Back Drive Protection
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Available in the Texas Instruments NanoFree Package
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Max t_pd of 4.2 ns at 3.3 V
Low Power Consumption, 10-μA Max I_CC
±24-mA Output Drive at 3.3 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
I_off Feature Supports Live Insertion, Partial-Power-Down Mode Operation and Back Drive Protection
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

This dual positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V V_CC operation.

When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This dual positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V V_CC operation.

When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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Technische Dokumentation

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Top-Dokumentation	Typ	Titel	Format-Optionen
*	Datenblatt	Dual Positive-Edge-Triggered D-Type Flip-Flop, SN74LVC2G79 datasheet (Rev. E)		24.12.2013
	Anwendungshinweis	Power-Up Behavior of Clocked Devices (Rev. B)	PDF \| HTML	15.12.2022
	Application brief	Simplifying Solid-State Relay Designs With Logic	PDF \| HTML	08.01.2021

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