Produktdetails

CPU 32-/64-bit Rating Military Operating temperature range (°C) -55 to 125
CPU 32-/64-bit Rating Military Operating temperature range (°C) -55 to 125
CFCBGA (GLP) 429 729 mm² (— mm × — mm)
  • High-Performance Fixed-Point Digital Signal
    Processor (DSP) SMJ320C62x™
    • 5-ns Instruction Cycle Time
    • 200-MHz Clock Rate
    • Eight 32-Bit Instructions/Cycle
    • 1600 Million Instructions per Second (MIPS)
  • 429-Pin Ball Grid Array (BGA) Package (GLP
    Suffix)
  • VelociTI™ Advanced Very-Long-Instruction-Word
    (VLIW) C62x DSP Core
    • Eight Highly-Independent Functional Units:
      • Six Arithmetic Logic Units (ALUs) (32-/40-
        Bit)
      • Two 16-Bit Multipliers (32-Bit Result)
    • Load-Store Architecture With 32 32-Bit
      General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-, 16-, 32-Bit Data)
    • 8-Bit Overflow Protection
    • Saturation
    • Bit-Field Extract, Set, Clear
    • Bit-Counting
    • Normalization
  • 7Mb On-Chip SRAM
    • 3Mb Internal Program/Cache (96K 32-Bit
      Instructions)
    • 4Mb Dual-Access Internal Data (512KB)
    • Organized as Two 256KB Blocks for Improved
      Concurrency
  • Flexible Phase-Locked-Loop (PLL) Clock
    Generator
  • 32-Bit External Memory Interface (EMIF)
    • Glueless Interface to Synchronous Memories:
      SDRAM or SBSRAM
    • Glueless Interface to Asynchronous Memories:
      SRAM and EPROM
    • 52MB Addressable External Memory Space
  • Four-Channel Bootloading Direct-Memory-Access
    (DMA) Controller With an Auxiliary Channel
  • 32-Bit Expansion Bus − Glueless/Low-Glue
  • Glueless/Low-Glue Interface to Popular
    Synchronous or Asynchronous Microprocessor
    Buses
  • Master/Slave Functionality
  • Glueless Interface to Synchronous FIFOs and
    Asynchronous Peripherals
  • Three Multichannel Buffered Serial Ports
    (McBSPs)
    • Direct Interface to T1/E1, MVIP, SCSA
      Framers
    • ST-Bus-Switching Compatible
    • Up to 256 Channels Each
    • AC97-Compatible
    • Serial-Peripheral Interface (SPI) Compatible
      (Motorola®)
  • Two 32-Bit General-Purpose Timers
  • IEEE-1149.1 (JTAG(2)) Boundary-Scan-
    Compatible
  • 0.15-µm/5-Level Metal Process
    • CMOS Technology
  • 3.3-V I/Os, 1.5-V Internal

All trademarks are the property of their respective owners.

  • High-Performance Fixed-Point Digital Signal
    Processor (DSP) SMJ320C62x™
    • 5-ns Instruction Cycle Time
    • 200-MHz Clock Rate
    • Eight 32-Bit Instructions/Cycle
    • 1600 Million Instructions per Second (MIPS)
  • 429-Pin Ball Grid Array (BGA) Package (GLP
    Suffix)
  • VelociTI™ Advanced Very-Long-Instruction-Word
    (VLIW) C62x DSP Core
    • Eight Highly-Independent Functional Units:
      • Six Arithmetic Logic Units (ALUs) (32-/40-
        Bit)
      • Two 16-Bit Multipliers (32-Bit Result)
    • Load-Store Architecture With 32 32-Bit
      General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-, 16-, 32-Bit Data)
    • 8-Bit Overflow Protection
    • Saturation
    • Bit-Field Extract, Set, Clear
    • Bit-Counting
    • Normalization
  • 7Mb On-Chip SRAM
    • 3Mb Internal Program/Cache (96K 32-Bit
      Instructions)
    • 4Mb Dual-Access Internal Data (512KB)
    • Organized as Two 256KB Blocks for Improved
      Concurrency
  • Flexible Phase-Locked-Loop (PLL) Clock
    Generator
  • 32-Bit External Memory Interface (EMIF)
    • Glueless Interface to Synchronous Memories:
      SDRAM or SBSRAM
    • Glueless Interface to Asynchronous Memories:
      SRAM and EPROM
    • 52MB Addressable External Memory Space
  • Four-Channel Bootloading Direct-Memory-Access
    (DMA) Controller With an Auxiliary Channel
  • 32-Bit Expansion Bus − Glueless/Low-Glue
  • Glueless/Low-Glue Interface to Popular
    Synchronous or Asynchronous Microprocessor
    Buses
  • Master/Slave Functionality
  • Glueless Interface to Synchronous FIFOs and
    Asynchronous Peripherals
  • Three Multichannel Buffered Serial Ports
    (McBSPs)
    • Direct Interface to T1/E1, MVIP, SCSA
      Framers
    • ST-Bus-Switching Compatible
    • Up to 256 Channels Each
    • AC97-Compatible
    • Serial-Peripheral Interface (SPI) Compatible
      (Motorola®)
  • Two 32-Bit General-Purpose Timers
  • IEEE-1149.1 (JTAG(2)) Boundary-Scan-
    Compatible
  • 0.15-µm/5-Level Metal Process
    • CMOS Technology
  • 3.3-V I/Os, 1.5-V Internal

All trademarks are the property of their respective owners.

The SMJ320C6203 device is part of the SMJ320C62x fixed-point DSP generation in the SMJ320C6000 DSP platform. The C62x DSP devices are based on the high-performance, advanced VelociTI VLIW architecture developed by TI, making these DSPs an excellent choice for multichannel and multifunction applications.

The SMJ320C62x DSP offers cost-effective solutions to high-performance DSP-programming challenges. The SMJ320C6203 has a performance capability of up to 1600 MIPS at a clock rate of 200 MHz. The C6203 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly-independent functional units.

The eight functional units provide six ALUs for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6203 can produce two multiply-accumulates (MACs) per cycle for a total of 400 million MACs per second (MMACS). The C6203 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The C6203 device program memory consists of two blocks, with a 256KB block configured as memory-mapped program space, and the other 128KB block user-configurable as cache or memory-mapped program space. Data memory for the C6203 consists of two 256KB blocks of RAM.

The C6203 device has a powerful and diverse set of peripherals. The peripheral set includes three McBSPs, two general-purpose timers, a 32-bit expansion bus that offers ease of interface to synchronous or asynchronous industry-standard host bus protocols, and a glueless 32-bit EMIF capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.

The C62x devices have a complete set of development tools that includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.

The SMJ320C6203 device is part of the SMJ320C62x fixed-point DSP generation in the SMJ320C6000 DSP platform. The C62x DSP devices are based on the high-performance, advanced VelociTI VLIW architecture developed by TI, making these DSPs an excellent choice for multichannel and multifunction applications.

The SMJ320C62x DSP offers cost-effective solutions to high-performance DSP-programming challenges. The SMJ320C6203 has a performance capability of up to 1600 MIPS at a clock rate of 200 MHz. The C6203 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly-independent functional units.

The eight functional units provide six ALUs for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6203 can produce two multiply-accumulates (MACs) per cycle for a total of 400 million MACs per second (MMACS). The C6203 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The C6203 device program memory consists of two blocks, with a 256KB block configured as memory-mapped program space, and the other 128KB block user-configurable as cache or memory-mapped program space. Data memory for the C6203 consists of two 256KB blocks of RAM.

The C6203 device has a powerful and diverse set of peripherals. The peripheral set includes three McBSPs, two general-purpose timers, a 32-bit expansion bus that offers ease of interface to synchronous or asynchronous industry-standard host bus protocols, and a glueless 32-bit EMIF capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.

The C62x devices have a complete set of development tools that includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.

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Technische Dokumentation

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Top-Dokumentation Typ Titel Format-Optionen Neueste englische Version herunterladen Datum
* Datenblatt SMJ320C6203 Fixed-Point Digital Signal Processor datasheet (Rev. A) PDF | HTML 24.05.2016
* Errata TMS320C6203, TMS320C6203B DSPs Silicon Errata (Silicon Rev. 1.x, 2.x, 3.0, 3.1) (Rev. L) 16.02.2004
* SMD SMJ320C6203 SMD 5962-00510 21.06.2016
Anwendungshinweis Introduction to TMS320C6000 DSP Optimization 06.10.2011
Weitere Dokumente SMJ320C6203GLPM20/5962-0051001QXA (Rev. A) 03.05.2002
Weitere Dokumente Military C6000 DSPs (Rev. A) 08.05.2000

Design und Entwicklung

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Lauterbach‘s TRACE32® tools are a suite of leading-edge hardware and software components that enables developers to analyze, optimize and certify all kinds of single- or multi-core Digital Signal processors (DSPs) which are a popular choice for audio and video processing as well as radar data (...)

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Simulationsmodell

SMJ320C6203 GLP BSDL Model

SGUM004.ZIP (4 KB) - BSDL-Modell
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