The DS90UB914A-Q1 device offers an FPD-Link III interface with a high-speed forward
channel and a bidirectional control channel for data transmission over a single coaxial cable or
differential pair. The DS90UB914A-Q1 device incorporates differential signaling on both the
high-speed forward channel and bidirectional control channel data paths. The deserializer is
targeted for connections between imagers and video processors in an ECU (Electronic Control Unit).
This device is ideally suited for driving video data requiring up to 12-bit pixel depth plus two
synchronization signals along with bidirectional control channel bus.
The deserializer features a multiplexer to allow selection between two input imagers, one
active at a time. The primary video transport converts 10-bit or 12-bit data to a single high-speed
serial stream, along with a separate low latency bidirectional control channel transport that
accepts control information from an I2C port and is independent of video blanking period.
Using TI’s embedded clock technology allows transparent full-duplex
communication over a single differential pair, carrying asymmetrical-bidirectional control channel
information. This single serial stream simplifies transferring a wide data bus over PCB traces and
cable by eliminating the skew problems between parallel data and clock paths. This significantly
saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and
connector size and pins. In addition, the Deserializer inputs provide adaptive equalization to
compensate for loss from the media over longer distances. Internal DC-balanced encoding/decoding is
used to support AC-coupled interconnects.
The DS90UB914A-Q1 device offers an FPD-Link III interface with a high-speed forward
channel and a bidirectional control channel for data transmission over a single coaxial cable or
differential pair. The DS90UB914A-Q1 device incorporates differential signaling on both the
high-speed forward channel and bidirectional control channel data paths. The deserializer is
targeted for connections between imagers and video processors in an ECU (Electronic Control Unit).
This device is ideally suited for driving video data requiring up to 12-bit pixel depth plus two
synchronization signals along with bidirectional control channel bus.
The deserializer features a multiplexer to allow selection between two input imagers, one
active at a time. The primary video transport converts 10-bit or 12-bit data to a single high-speed
serial stream, along with a separate low latency bidirectional control channel transport that
accepts control information from an I2C port and is independent of video blanking period.
Using TI’s embedded clock technology allows transparent full-duplex
communication over a single differential pair, carrying asymmetrical-bidirectional control channel
information. This single serial stream simplifies transferring a wide data bus over PCB traces and
cable by eliminating the skew problems between parallel data and clock paths. This significantly
saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and
connector size and pins. In addition, the Deserializer inputs provide adaptive equalization to
compensate for loss from the media over longer distances. Internal DC-balanced encoding/decoding is
used to support AC-coupled interconnects.