48-pin (PFB) package image

SRC4392IPFB 正在供货

高端组合采样速率转换器

定价

数量 价格
+

其他包装数量 | 包装选项 这些产品完全相同,仅包装类型不同

SRC4392IPFBR 正在供货 custom-reels 定制 可提供定制卷带
包装数量 | 包装 1,000 | LARGE T&R
库存
数量 | 价格 1ku | +

质量信息

等级 Catalog
RoHS
REACH
引脚镀层/焊球材料 NIPDAU
MSL 等级/回流焊峰值温度 Level-2-260C-1 YEAR
质量、可靠性
和封装信息

包含信息:

  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
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更多制造信息

包含信息:

  • 制造厂地点
  • 封装厂地点
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出口管制分类

*仅供参考

  • 美国 ECCN:EAR99

封装信息

封装 | 引脚 TQFP (PFB) | 48
工作温度范围 (°C) -40 to 85
包装数量 | 包装 250 | JEDEC TRAY (5+1)

SRC4392 的特性

  • Two-Channel Asynchronous Sample Rate Converter (SRC)
    • Dynamic Range with –60dB Input (A-Weighted): 144dB typical
    • Total Harmonic Distortion and Noise (THD+N) with Full-Scale Input: –140dB typical
    • Supports Audio Input and Output Data Word Lengths Up to 24 Bits
    • Supports Input and Output Sampling Frequencies Up to 216kHz
    • Automatic Detection of the Input-to-Output Sampling Ratio
    • Wide Input-to-Output Conversion Range:
      16:1 to 1:16 Continuous
    • Excellent Jitter Attenuation Characteristics
    • Digital De-Emphasis Filtering for 32kHz, 44.1kHz, and 48kHz Input Sampling Rates
    • Digital Output Attenuation and Mute Functions
    • Output Word Length Reduction
    • Status Registers and Interrupt Generation for Sampling Ratio and Ready Flags
  • Digital Audio Interface Transmitter (DIT)
    • Supports Sampling Rates Up to 216kHz
    • Includes Differential Line Driver and
      CMOS Buffered Outputs
    • Block-Sized Data Buffers for Both Channel Status and User Data
    • Status Registers and Interrupt Generation for Flag and Error Conditions
  • User-Selectable Serial Host Interface: SPI or Philips I2C™
    • Provides Access to On-Chip Registers and Data Buffers

    U.S. Patent No. 7,262,716

  • Digital Audio Interface Receiver (DIR)
    • PLL Lock Range Includes Sampling Rates from 20kHz to 216kHz
    • Includes Four Differential Input Line Receivers and an Input Multiplexer
    • Bypass Multiplexer Routes Line Receiver Outputs to Line Driver and Buffer Outputs
    • Block-Sized Data Buffers for Both Channel Status and User Data
    • Automatic Detection of Non-PCM Audio Streams (DTS CD/LD and IEC 61937 formats)
    • Audio CD Q-Channel Sub-Code Decoding and Data Buffer
    • Status Registers and Interrupt Generation for Flag and Error Conditions
    • Low Jitter Recovered Clock Output
  • Two Audio Serial Ports (Ports A and B)
    • Synchronous Serial Interface to External Signal Processors, Data Converters, and Logic
    • Slave or Master Mode Operation with Sampling Rates up to 216kHz
    • Supports Left-Justified, Right-Justified, and Philips I2S™ Data Formats
    • Supports Audio Data Word Lengths Up to
      24 Bits
  • Four General-Purpose Digital Outputs
    • Multifunction Programmable Via Control Registers
  • Extensive Power-Down Support
    • Functional Blocks May Be Disabled Individually When Not In Use
  • Operates From +1.8V Core and +3.3V I/O Power Supplies
  • Packages:
    • QFN-40
    • Small TQFP-48 Package, Compatible with the SRC4382 and DIX4192

SRC4392 的说明

The SRC4392 is a highly-integrated CMOS device designed for use in professional and broadcast digital audio systems. The SRC4392 combines a high-performance, two-channel, asynchronous sample rate converter (SRC) with a digital audio interface receiver (DIR) and transmitter (DIT), two audio serial ports, and flexible distribution logic for interconnection of the function block data and clocks.

The DIR and DIT are compatible with the AES3, S/PDIF, IEC 60958, and EIAJ CP-1201 interface standards. The audio serial ports, DIT, and SRC may be operated at sampling rates up to 216kHz. The DIR lock range includes sampling rates from 20kHz to 216kHz.

The SRC4392 is configured using on-chip control registers and data buffers, which are accessed through either a 4-wire serial peripheral interface (SPI) port, or a 2-wire Philips I2C bus interface. Status registers provide access to a variety of flag and error bits, which are derived from the various function blocks. An open drain interrupt output pin is provided, and is supported by flexible interrupt reporting and mask options via control register settings. A master reset input pin is provided for initialization by a host processor or supervisory functions.

The SRC4392 requires a +1.8V core logic supply, in addition to a +3.3V supply for powering portions of the DIR, DIT, and line driver and receiver functions. A separate logic I/O supply supports operation from +1.65V to +3.6V, providing compatibility with low voltage logic interfaces typically found on digital signal processors and programmable logic devices. The SRC4392 is available in a QFN-40 and a lead-free, TQFP-48 package. The TQFN-48 is pin- and register-compatible with the Texas Instruments SRC4382 and DIX4192 products.

定价

数量 价格
+

其他包装数量 | 包装选项 这些产品完全相同,仅包装类型不同

SRC4392IPFBR 正在供货 custom-reels 定制 可提供定制卷带
包装数量 | 包装 1,000 | LARGE T&R
库存
数量 | 价格 1ku | +

包装方式

您可以根据器件数量选择不同的包装方式,包括完整卷带、定制卷带、剪切带、管装或托盘。

定制卷带是从整盘卷带上剪下来的具有连续长度的剪切带,是一种可以对特定数量提供产品批次及生产日期跟踪的包装方式。根据行业标准,使用黄铜垫片在剪切带两端各连接一个 18 英寸的引带和尾带,以直接送入自动组装机。涉及定制卷带的 TI 订单将包含卷带费用。

剪切带是从整盘卷带上剪下来的特定长度的编带。根据所申请器件数量的不同,TI 可能会使用多条剪切带或多个盒子进行包装。

TI 通常会根据库存情况选择将管装托盘器件以盒装或者管装或托盘形式发货。所有器件均会按照 TI 内部规定的静电放电和湿敏等级保护要求进行包装。

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可提供批次和生产日期代码选项

您可在购物车中添加器件数量以开始结算流程,并查看现有库存中可选择批次或生产日期代码的选项。

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