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SN74ALVCH16524

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具有三态输出的 18 位寄存总线收发器

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SN74ALVCH16524

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产品详情

Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Number of channels 18 IOL (max) (mA) 24 IOH (max) (mA) -24 Input type LVTTL Output type LVTTL Features Balanced outputs, Bus-hold, Ultra high speed (tpd <5ns) Technology family ALVC Rating Catalog Operating temperature range (°C) -40 to 85
Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Number of channels 18 IOL (max) (mA) 24 IOH (max) (mA) -24 Input type LVTTL Output type LVTTL Features Balanced outputs, Bus-hold, Ultra high speed (tpd <5ns) Technology family ALVC Rating Catalog Operating temperature range (°C) -40 to 85
SSOP (DL) 56 190.647 mm² 18.42 x 10.35
  • Member of the Texas Instruments Widebus™ Family
  • UBT™ Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enable Mode
  • Operates From 1.65-V to 3.6-V
  • Max tpd of 3.2 ns at 3.3-V
  • ±24-mA Output Drive at 3.3-V
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

Widebus, UBT are trademarks of Texas Instruments.
  • Member of the Texas Instruments Widebus™ Family
  • UBT™ Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enable Mode
  • Operates From 1.65-V to 3.6-V
  • Max tpd of 3.2 ns at 3.3-V
  • ±24-mA Output Drive at 3.3-V
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

Widebus, UBT are trademarks of Texas Instruments.

This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V VCC operation.

Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\) and clock-enable (CLKENBA\) inputs. For the A-to-B data flow, the data flows through a single buffer. The B-to-A data can flow through a four-stage pipeline register path, or through a single register path, depending on the state of the select (SEL\) input.

Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input, provided that the appropriate CLKENBA\ input is low. The B-to-A data transfer is synchronized with CLK.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V VCC operation.

Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\) and clock-enable (CLKENBA\) inputs. For the A-to-B data flow, the data flows through a single buffer. The B-to-A data can flow through a four-stage pipeline register path, or through a single register path, depending on the state of the select (SEL\) input.

Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input, provided that the appropriate CLKENBA\ input is low. The B-to-A data transfer is synchronized with CLK.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
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类型 标题 下载最新的英语版本 日期
* 数据表 SN74ALVCH16524 数据表 (Rev. E) 2004年 9月 1日
选择指南 Logic Guide (Rev. AB) 2017年 6月 12日
应用手册 Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
选择指南 逻辑器件指南 2014 (Rev. AA) 最新英语版本 (Rev.AB) 2014年 11月 17日
用户指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
应用手册 Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
应用手册 TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
用户指南 ALVC Advanced Low-Voltage CMOS Including SSTL, HSTL, And ALB (Rev. B) 2002年 8月 1日
更多文献资料 Standard Linear & Logic for PCs, Servers & Motherboards 2002年 6月 13日
应用手册 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002年 5月 22日
应用手册 Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) 1999年 9月 8日
应用手册 TI SN74ALVC16835 Component Specification Analysis for PC100 1998年 8月 3日
应用手册 Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A) 1998年 5月 13日
应用手册 Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 1997年 12月 1日
应用手册 Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
应用手册 CMOS Power Consumption and CPD Calculation (Rev. B) 1997年 6月 1日
应用手册 Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
应用手册 Live Insertion 1996年 10月 1日
应用手册 Understanding Advanced Bus-Interface Products Design Guide 1996年 5月 1日

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包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

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