产品详情

Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Number of channels 8 IOL (max) (mA) 7.8 IOH (max) (mA) -7.8 Input type CMOS Output type CMOS Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Technology family HC Rating Military Operating temperature range (°C) -55 to 125
Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Number of channels 8 IOL (max) (mA) 7.8 IOH (max) (mA) -7.8 Input type CMOS Output type CMOS Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Technology family HC Rating Military Operating temperature range (°C) -55 to 125
CDIP (J) 24 425.45 mm² 31.75 x 13.4
  • 2-V to 6-V VCC Operation (CD54HC646)
  • 4.5-V to 5.5-V VCC Operation (CD74HCT646)
  • Wide Operating Temperature Range of –55°C to 125°C
  • Balanced Propagation Delays and Transition Times
  • Standard Outputs Drive Up To 15 LS-TTL Loads
  • Significant Power Reduction Compared to LS-TTL Logic ICs
  • Inputs Are TTL-Voltage Compatible (CD74HCT646)
  • Independent Registers for A and B Buses
  • Multiplexed Real-Time and Stored Data
  • True Data Paths

  • 2-V to 6-V VCC Operation (CD54HC646)
  • 4.5-V to 5.5-V VCC Operation (CD74HCT646)
  • Wide Operating Temperature Range of –55°C to 125°C
  • Balanced Propagation Delays and Transition Times
  • Standard Outputs Drive Up To 15 LS-TTL Loads
  • Significant Power Reduction Compared to LS-TTL Logic ICs
  • Inputs Are TTL-Voltage Compatible (CD74HCT646)
  • Independent Registers for A and B Buses
  • Multiplexed Real-Time and Stored Data
  • True Data Paths

The CD54HC646 and CD74HCT646 consist of bus-transceiver circuits with 3-state outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with these devices.

Output-enable (OE\) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode, data present at the high-impedance port can be stored in either or both registers.

The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR determines which bus receives data when OE\ is active (low). In the isolation mode (OE\ high), A data can be stored in one register and/or B data can be stored in the other register.

When an output function is disabled, the input function still is enabled and can be used to store data. Only one of the two buses, A or B, can be driven at a time.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The CD54HC646 and CD74HCT646 consist of bus-transceiver circuits with 3-state outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with these devices.

Output-enable (OE\) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode, data present at the high-impedance port can be stored in either or both registers.

The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR determines which bus receives data when OE\ is active (low). In the isolation mode (OE\ high), A data can be stored in one register and/or B data can be stored in the other register.

When an output function is disabled, the input function still is enabled and can be used to store data. Only one of the two buses, A or B, can be driven at a time.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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类型 标题 下载最新的英语版本 日期
* 数据表 CD54HC646, CD74HCT646 数据表 (Rev. B) 2003年 4月 25日
* SMD CD54HC646 SMD 5962-86885 2016年 6月 21日
应用手册 Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
选择指南 Logic Guide (Rev. AB) 2017年 6月 12日
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选择指南 逻辑器件指南 2014 (Rev. AA) 最新英语版本 (Rev.AB) 2014年 11月 17日
用户指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
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应用手册 Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
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应用手册 SN54/74HCT CMOS Logic Family Applications and Restrictions 1996年 5月 1日
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