主页 数据转换器 模数转换器 (ADC) 高速 ADC (≥10MSPS)
主页
数据转换器
模数转换器 (ADC)
高速 ADC (≥10MSPS)

ADC08D502

正在供货

双通道、8 位、500MSPS 模数转换器 (ADC)

立即订购
数据表

ADC08D502

正在供货
数据表 立即订购

产品详情

Sample rate (max) (Msps) 500 Resolution (Bits) 8 Number of input channels 2 Interface type Parallel LVDS Analog input BW (MHz) 1700 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 0.87 Power consumption (typ) (mW) 1400 Architecture Folding Interpolating SNR (dB) 48 ENOB (Bits) 7.5 SFDR (dB) 55 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 500 Resolution (Bits) 8 Number of input channels 2 Interface type Parallel LVDS Analog input BW (MHz) 1700 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 0.87 Power consumption (typ) (mW) 1400 Architecture Folding Interpolating SNR (dB) 48 ENOB (Bits) 7.5 SFDR (dB) 55 Operating temperature range (°C) -40 to 85 Input buffer No
HLQFP (NNB) 128 484 mm² 22 x 22
  • Internal Sample-and-Hold
  • Single +1.9V ±0.1V Operation
  • Choice of SDR or DDR Output Clocking
  • Multiple ADC Synchronization Capability
  • Specified No Missing Codes
  • Serial Interface for Extended Control
  • Fine Adjustment of Input Full-Scale Range and Offset
  • Duty Cycle Corrected Sample Clock

Key Specifications

  • Resolution: 8 Bits
  • Max Conversion Rate: 500 MSPS (min)
  • Bit Error Rate: 10-18 (typ)
  • ENOB @ 250 MHz Input: 7.5 Bits (typ)
  • DNL: ±0.15 LSB (typ)
  • Power Consumption
    • Operating: 1.4 W (typ)
    • Power Down Mode: 3.5 mW (typ)

All trademarks are the property of their respective owners.

  • Internal Sample-and-Hold
  • Single +1.9V ±0.1V Operation
  • Choice of SDR or DDR Output Clocking
  • Multiple ADC Synchronization Capability
  • Specified No Missing Codes
  • Serial Interface for Extended Control
  • Fine Adjustment of Input Full-Scale Range and Offset
  • Duty Cycle Corrected Sample Clock

Key Specifications

  • Resolution: 8 Bits
  • Max Conversion Rate: 500 MSPS (min)
  • Bit Error Rate: 10-18 (typ)
  • ENOB @ 250 MHz Input: 7.5 Bits (typ)
  • DNL: ±0.15 LSB (typ)
  • Power Consumption
    • Operating: 1.4 W (typ)
    • Power Down Mode: 3.5 mW (typ)

All trademarks are the property of their respective owners.

The ADC08D502 is a dual, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 500 MSPS. Consuming a typical 1.4 Watts at 500 MSPS from a single 1.9 Volt supply, this device is specified to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.5 ENOB with a 250 MHz input signal and a 500 MHz sample rate while providing a 10-18 B.E.R. Output formatting is offset binary and the LVDS digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V.

Each converter has a 1:2 demultiplexer that feeds two LVDS buses and reduces the output data rate on each bus to half the sampling rate.

The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad HLQFP and operates over the Industrial (-40°C ≤ TA ≤ +85°C) temperature range.

The ADC08D502 is a dual, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 500 MSPS. Consuming a typical 1.4 Watts at 500 MSPS from a single 1.9 Volt supply, this device is specified to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.5 ENOB with a 250 MHz input signal and a 500 MHz sample rate while providing a 10-18 B.E.R. Output formatting is offset binary and the LVDS digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V.

Each converter has a 1:2 demultiplexer that feeds two LVDS buses and reduces the output data rate on each bus to half the sampling rate.

The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad HLQFP and operates over the Industrial (-40°C ≤ TA ≤ +85°C) temperature range.
filter 查找其他 高速 ADC (≥10MSPS)
下载 观看带字幕的视频 视频

技术文档

star =有关此产品的 TI 精选热门文档
未找到结果。请清除搜索并重试。
查看全部 1
类型 标题 下载最新的英语版本 日期
* 数据表 ADC08D502 Hi Perf, Low Power, Dual 8-Bit, 500 MSPS A/D Conv 数据表 (Rev. A) 2013年 4月 2日

设计和开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

仿真模型

ADC08D502 IBIS Model

SNOM336.ZIP (9 KB) - IBIS Model
下载
模拟工具

PSPICE-FOR-TI — 适用于 TI 设计和模拟工具的 PSpice®

PSpice® for TI 可提供帮助评估模拟电路功能的设计和仿真环境。此功能齐全的设计和仿真套件使用 Cadence® 的模拟分析引擎。PSpice for TI 可免费使用，包括业内超大的模型库之一，涵盖我们的模拟和电源产品系列以及精选的模拟行为模型。

借助 PSpice for TI 的设计和仿真环境及其内置的模型库，您可对复杂的混合信号设计进行仿真。创建完整的终端设备设计和原型解决方案，然后再进行布局和制造，可缩短产品上市时间并降低开发成本。

在 PSpice for TI 设计和仿真工具中，您可以搜索 TI (...)
发送申请
封装 引脚 CAD 符号、封装和 3D 模型
HLQFP (NNB) 128 Ultra Librarian
应遵守 TI 评估类商品的标准条款与条件。

订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

推荐产品可能包含与 TI 此产品相关的参数、评估模块或参考设计。

支持和培训

视频