ADC08B200
- Single-Ended Input
- Selectable Capture Buffer Size
- PLL for Clock Multiplication
- Reference Ladder Top and Bottom Accessible
- Linear Power Scaling with Sample Rate
- FPGA Training Pattern
- AEC-Q100 Grade 2 Qualified
- Power-Down Feature
Key Specifications
- Resolution 8 Bits
- Maximum Sampling Frequency 200 MSPS (min)
- DNL ±0.4 LSB (typ)
- ENOB (fIN= 49 MHz) 7.2 bits (typ)
- THD (fIN= 49 MHz) −53 dBc (typ)
- Power Consumption
- Operating (50 MHz) Input 2 mW / Msps (typ)
- Power Down 2.15 mW (typ)
(PLL Bypassed)
All trademarks are the property of their respective owners.
The ADC08B200 is a high speed analog-to-digital converter (ADC) with an integrated capture buffer. The 8-bit, 200 MSPS A/D core is based upon the proven ADC08200 with integrated track-and-hold and is optimized for low power consumption. This device contains a selectable size capture buffer of up to 1,024 bytes that allows fast capture of an input signal with a slower readout rate. An on-chip clock PLL circuit provides the option of on-chip clock rate multiplication to provide the high speed sampling clock.
The ADC08B200 is resistant to latch-up and the outputs are short-circuit proof. The top and bottom of the ADC08B200's reference ladder are available for connections, enabling a wide range of input possibilities. The digital outputs are TTL/CMOS compatible with a separate output power supply pin to support interfacing with 2.7V to 3.3V logic. The digital inputs and outputs are low voltage TTL/CMOS compatible and the output data format is straight binary.
The ADC08B200Q runs on an Automotive Grade Flow and is AEC-Q100 Grade 2 Qualified.
The ADC08B200 is offered in a 48-pin plastic package (TQFP) and is specified over the extended industrial temperature range of −40°C to +105°C. An evaluation board is available to assist in the easy evaluation of the ADC08B200.
技术文档
类型 | 标题 | 下载最新的英语版本 | 日期 | |||
---|---|---|---|---|---|---|
* | 数据表 | ADC08B200 / ADC08B200Q 8-Bit, 200 MSPS A/D Converter with Capture Buffer 数据表 (Rev. F) | 2013年 4月 2日 | |||
应用手册 | Adaptive Speed Control for Automotive Systems | 2007年 11月 20日 |
设计和开发
如需其他信息或资源,请点击以下任一标题进入详情页面查看(如有)。
PSPICE-FOR-TI — 适用于 TI 设计和模拟工具的 PSpice®
借助 PSpice for TI 的设计和仿真环境及其内置的模型库,您可对复杂的混合信号设计进行仿真。创建完整的终端设备设计和原型解决方案,然后再进行布局和制造,可缩短产品上市时间并降低开发成本。
在 PSpice for TI 设计和仿真工具中,您可以搜索 TI (...)
封装 | 引脚 | CAD 符号、封装和 3D 模型 |
---|---|---|
TQFP (PFB) | 48 | Ultra Librarian |
订购和质量
- RoHS
- REACH
- 器件标识
- 引脚镀层/焊球材料
- MSL 等级/回流焊峰值温度
- MTBF/时基故障估算
- 材料成分
- 鉴定摘要
- 持续可靠性监测
- 制造厂地点
- 封装厂地点