LM5123-Q1 2.2MHz 宽 VIN 低 IQ 同步升压控制器，具有 VOUT 跟踪功能
- ZHCSMW2B December 2021 – December 2022 LM5123-Q1
  
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LM5123-Q1 2.2MHz 宽 VIN 低 IQ 同步升压控制器，具有 VOUT 跟踪功能

本资源的原文使用英文撰写。为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

符合面向汽车应用的 AEC-Q100 标准
- 温度等级 1：–40°C 至 +125°C，T_A
提供功能安全
- 可帮助进行功能安全系统设计的文档
适用于宽工作电压范围的汽车类电池供电应用
- 3.8V 至 42V 输入电压工作范围
- 5V 至 20V 或 15V 至 57V 的动态可编程 VOUT
- BIAS 电压大于等于 3.8V 时最小升压输入为 0.8V
- V_SUPPLY > V_LOAD 时进行旁路操作
最小电池消耗
- 关断电流 ≤ 3μA
- 自动模式转换
- 睡眠模式下的电池消耗 ≤ 11μA（旁路操作，电荷泵关闭）
- 睡眠模式下的电池消耗 ≤ 38μA（旁路操作，电荷泵打开）
- 睡眠模式下的偏置电流 I_Q ≤ 13μA（跳跃模式）
- 强大的 5V MOSFET 驱动器
解决方案尺寸小、成本低
- 最大开关频率：2.2MHz
- 内部自举二极管
- 在 VIN 范围内峰值电流限制保持恒定
- 支持 DCR 电感器电流感应
- 具有可湿性侧面的 QFN-20 封装
避免 AM 频带干扰和串扰
- 可选的时钟同步
- 开关频率范围为 100kHz 至 2.2MHz
- 可选开关模式（FPWM、二极管仿真和跳跃模式）
降低 EMI
- 可选可编程扩展频谱
- 无引线封装
可编程性和灵活性
- 动态 VOUT 跟踪
- 动态开关频率编程
- 可编程线路 UVLO
- 可调软启动
- 自适应死区时间
- PGOOD 指示器
集成型保护特性
- 逐周期峰值电流限制
- 过压保护
- HB-SW 短路保护
- 热关断

2 应用

3 说明

LM5123-Q1 器件是一款采用峰值电流模式控制的宽输入范围同步升压控制器。

器件信息

器件型号	封装⁽¹⁾	封装尺寸（标称值）
LM5123-Q1	QFN (20)	3.5mm x 3.5mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。

典型应用

4 Revision History

Changes from Revision A (December 2021) to Revision B (January 2022)

Updated Bias current and battery drain in deep sleepGo
Updated overvoltage (OVP) and undervoltage threshold (PGOOD)Go
Updated dead timeGo
Updated HB diode resistanceGo
Updated VOUT regulation target voltagesGo

Changes from Revision * (December 2020) to Revision A (December 2021)

将文档状态从“预告信息”更改为“量产数据”Go

5 说明（续）

该器件采用低关断 I_Q 和低 I_Q 睡眠模式，可尽可能减少无负载和轻负载条件下的电池消耗。该器件还支持旁路模式的超低 I_Q 深度睡眠模式，当电源电压大于升压输出调节目标时，无需外部旁路开关。可使用跟踪功能对此输出电压进行动态编程。

该器件的宽输入范围支持汽车冷启动和负载突降。当 BIAS 等于或大于 3.8V 时，最小输入电压可低至 0.8V。用户可通过外部电阻器对开关频率进行动态编程，编程范围为 100kHz 至 2.2MHz。2.2MHz 的开关频率可更大限度地降低 AM 频带干扰，并支持实现小解决方案尺寸和快速瞬态响应。与转换器架构相比，控制器架构简化了严苛环境温度条件下的热管理性能。

该器件具有内置的保护功能，例如在 V_IN 范围内保持恒定的峰值电流限制、过压保护和热关断功能。外部时钟同步、可编程展频调制以及具有超低寄生效应的无引线封装有助于降低 EMI 并避免串扰问题。附加功能包括线路 UVLO、FPWM、二极管仿真、DCR 电感器电流检测、可编程的软启动和电源正常状态指示器。

6 Pin Configuration and Functions

20-Pin QFN with Wettable Flanks RGR Package (Top View)

Table 6-1 Pin Functions

PIN		I/O⁽¹⁾	DESCRIPTION
NAME	NO.	I/O⁽¹⁾	DESCRIPTION
CSP	1	I	Current sense amplifier input. The pin operates as the positive input pin.
CSN	2	I	Current sense amplifier input. The pin operates as the negative input pin.
VOUT/SENSE	3	I	Output voltage sensing pin. An internal feedback resistor voltage divider is connected from the pin to AGND. Connect a 0.1-μF local VOUT capacitor from the pin to ground.
VOUT/SENSE	3	I	High-side MOSFET drain voltage sensing pin. Connect the pin to the drain of the high-side MOSFET through a short, low inductance path.
PGOOD	4	O	Power-good indicator with open-drain output stage. The pin is grounded when the output voltage is less than the undervoltage threshold. The pin can be left floating if not used.
HO	5	O	High-side gate driver output. Connect directly to the gate of the high-side N-channel MOSFET through a short, low inductance path.
SW	6	P	Switching node connection and the high-side MOSFET source voltage sensing pin. Connect directly to the source of the high-side N-channel MOSFET and the drain of the low-side N-channel MOSFET through a short, low inductance path. Connect to PGND for non-synchronous boost configuration.
HB	7	P	High-side driver supply for bootstrap gate drive. Boot diode is internally connected from VCC to the pin. Connect a 0.1-μF capacitor between the pin and SW. Connect to VCC for non-synchronous boost configuration.
BIAS	8	P	Supply voltage input to the VCC regulator. Connect a 1-μF local BIAS capacitor from the pin to ground.
VCC	9	P	Output of the internal VCC regulator and supply voltage input of the internal MOSFET drivers. Connect a 4.7-μF capacitor between the pin and PGND.
PGND	10	G	Power ground pin. Connect directly to the source of the low-side N-channel MOSFET and the power ground plane through a short, low inductance path.
LO	11	O	Low-side gate driver output. Connect directly to the gate of the low-side N-channel MOSFET through a short, low inductance path.
MODE	12	I	Device switching mode (FPWM, diode emulation, or skip) selection pin. The device is configured to skip mode if the pin is open or if a resistor that is greater than 500 kΩ is connected from the pin to AGND during initial power-on. The device is configured to FPWM mode by connecting the pin to VCC or if the pin voltage is greater than 2.0 V during power-on. The device is configured to diode emulation mode by connecting the pin to ground or the pin voltage is less than 0.4 V during initial power-on. The switching mode can be dynamically programmed between the FPWM and the DE mode during operation.
UVLO/EN	13	I	Enable pin. The pin enables/disables the device. If the pin is less than 0.35 V, the device shuts down. The pin must be raised above 0.65 V to enable the device.
UVLO/EN	13	I	Undervoltage lockout programming pin. The converter start-up and shutdown levels can be programmed by connecting the pin to the supply voltage through a resistor voltage divider. The low-side UVLO resistor must be connected to AGND. Connect to BIAS if not used.
SYNC/DITHER/VH/CP	14	I/O	Synchronization clock input. The internal oscillator can be synchronized to an external clock during operation. Connect to AGND if not used.
			Clock dithering/spread spectrum modulation frequency programming pin. If a capacitor is connected between the pin and AGND, the clock dithering/spread spectrum function is activated. During the dithering operation, the capacitor is charged and discharged with an internal 20-μA current source/sink. As the voltage on the pin ramps up and down, the oscillator frequency is modulated between –6% and +5% of the nominal frequency set by the RT resistor. The clock dithering/spread spectrum can be deactivated during operation by pulling down the pin to ground.
			VCC hold pin. If the pin is greater than 2.0 V, the device holds the VCC pin voltage when the EN pin is grounded, which helps to restart fast without reconfiguration.
			Charge pump enable pin. If the pin is greater than 2.0 V, the internal charge pump maintains the HB pin voltage above its HB UVLO threshold for bypass operation, which allows the high-side switch to turn on 100% during bypass operation.
RT	15	I	Switching frequency setting pin. If no external clock is applied to the SYNC pin, the switching frequency is programmed by a single resistor between the pin and AGND. Switching frequency is dynamically programmable during operation.
VREF/RANGE	16	I/O	1.0-V internal reference voltage output. Connect a 470-pF capacitor from the pin to AGND. The V_OUT regulation target can be programmed by connecting a resistor voltage divider from the pin to TRK. The resistance from the pin to AGND must be always greater than 20 kΩ if used. Connect the low-side resistor of the divider to AGND.
VREF/RANGE	16	I/O	V_OUT range selection pin. Lower V_OUT range (5 V to 20 V) is selected if the resistance from the pin to AGND is in the range of 75 kΩ and 100 kΩ during initial power-on. Upper VOUT range (15 V to 57 V) is selected if the resistance from the pin to AGND is in the range of 20 kΩ and 35 kΩ during initial power-on. Boost converter output voltage can be dynamically programmed within the pre-programmed range. The accuracy of the output voltage regulation is specified within the selected range.
SS	17	I/O	Soft-start time programming pin. An external capacitor and an internal current source set the ramp rate of the internal error amplifier reference during soft start. The device forces diode emulation during soft-start time.
TRK	18	I	Output regulation target programming pin. The V_OUT regulation target can be programmed by connecting the pin to VREF through a resistor voltage divider or by controlling the pin voltage directly from a D/A. The recommended operating range of the pin is from 0.25 V to 1.0 V.
AGND	19	G	Analog ground pin. Connect to the analog ground plane through a wide and short path.
COMP	20	O	Output of the internal transconductance error amplifier. Connect the loop compensation components between the pin and AGND.
EP	—		Exposed pad of the package. The EP must be soldered to a large analog ground plane to reduce thermal resistance.

(1) G = Ground, I = Input, O = Output, P = Power

7 Specifications

7.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range (unless otherwise specified)⁽¹⁾

		MIN	MAX	UNIT
Input⁽²⁾	BIAS to AGND	–0.3	50	V
	UVLO to AGND	–0.3	BIAS + 0.3
	CSP to AGND	–0.3	50
	CSP to CSN	–0.3	0.3
	VOUT to AGND	–0.3	65
	HB to AGND	–0.3	65
	HB to SW	–0.3	5.8⁽³⁾
	SW to AGND	-0.3	60
	SW to AGND (50ns)	–1
	MODE, SYNC, TRK to AGND	–0.3	5.5
	PGOOD to AGND	–0.3	VOUT + 0.3
	RT to AGND	–0.3	2.5
	PGND to AGND	–0.3	0.3
Output⁽²⁾	VCC to AGND	–0.3	5.8⁽³⁾	V
	HO to SW (50 ns)	–1
	LO to PGND (50 ns)	–1
	VREF, SS, COMP to AGND⁽⁴⁾	–0.3	5.5
Operating junction temperature, T_J⁽⁵⁾		–40	150	°C
Storage temperature, T_STG		–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) It is not allowed to apply an external voltage directly to VREF, COMP, SS, RT, LO, and HO pins.

(3) Operating lifetime is de-rated when the pin voltage is greater than 5.5 V.

(4) Maximum VREF pin sourcing current is 50 μA.

(5) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

7.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per AEC Q100-002⁽¹⁾ HBM ESD Classification Level 2		±2000	V
		Charged-device model (CDM), per AEC Q100-011 CDM ESD Classification Level C4B	All pins	±500
			Corner pins	±750

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

Over the recommended operating junction temperature range (unless otherwise specified)⁽¹⁾

		MIN	MAX	UNIT
V_{SUPPLY(BOOST)}	Boost converter input (when BIAS ≥ 3.8 V)	0.8	42	V
V_LOAD(BOOST)	Boost converter output	5	57
V_BIAS	BIAS input	3.8	42
V_UVLO	UVLO input	0	42
V_CSP, V_CSN	Current sense input	0.8	42
V_VOUT	Boost output sense	5	57
V_TRK	TRK input	0.25	1⁽³⁾
V_SYNC	Synchronization pulse input	0	5.25
f_SW	Typical switching frequency	100	2200	kHz
f_SYNC	Synchronization pulse frequency	200	2200	kHz
T_J	Operating junction temperature⁽²⁾	–40	150	°C

(1) Operating Ratings are conditions under the device is intended to be functional. For specifications and test conditions, see Electrical Characteristics.

(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

(3) The maximum TRK pin voltage is limited to 0.95 V when the upper V_OUT range is selected.

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		RGR (QFN)	UNIT
THERMAL METRIC⁽¹⁾		20 PINS	UNIT
R_qJA	Junction-to-ambient thermal resistance	43.3	°C/W
R_qJC(top)	Junction-to-case (top) thermal resistance	39.9	°C/W
R_qJB	Junction-to-board thermal resistance	17.8	°C/W
y_JT	Junction-to-top characterization parameter	0.8	°C/W
y_JB	Junction-to-board characterization parameter	17.8	°C/W
R_qJC(bot)	Junction-to-case (bottom) thermal resistance	5.3	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

Typical values correspond to T_J= 25°C. Minimum and maximum limits apply over T_J= –40°C to 125°C. Unless otherwise stated, V_BIAS= 12 V, V_VOUT= 12 V, R_T= 9.09 kΩ, R_VREF = 65 kΩ

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY CURRENT(BIAS, VCC, VOUT)
I_BIAS-SD	BIAS current in shutdown	V_UVLO= 0 V, V_OUT= 11.3 V		2.5	5	µA
I_BIAS-DS1	BIAS current in deep sleep (skip or diode emulation mode, charge pump off, VCC is supplied by BIAS)	V_UVLO= 2.5 V, V_TRK = 0.25 V, V_SYNC= 0 V, V_OUT= 12 V		10	16	µA
I_BIAS-DS2	BIAS current in deep sleep (FPWM mode, charge pump off, VCC is supplied by BIAS)	V_UVLO= 2.5 V, V_TRK = 0.25 V, V_SYNC= 0 V, V_OUT= 12 V		40	69	µA
I_BIAS-DS3	BIAS current in deep sleep (skip or diode emulation mode, charge pump on, VCC is supplied by BIAS)	V_UVLO= 2.5 V, V_TRK = 0.25 V, V_SYNC= 2.5 V, V_OUT= 12 V		32	60	µA
I_BIAS-DS4	BIAS current in deep sleep (FPWM mode, charge pump on, VCC is supplied by BIAS)	V_UVLO= 2.5 V, V_TRK = 0.25 V, V_SYNC= 2.5 V, V_OUT= 12 V		114	154	µA
I_BIAS-SLEEP	BIAS current in sleep (skip mode, VCC is supplied by BIAS)	V_UVLO= 2.5 V, V_TRK = 0.25 V, MODE = OPEN, V_OUT= 5 V		13	17.5	µA
I_BIAS-ACTIVE	BIAS current in active (non-switching, VCC is supplied by BIAS)	V_UVLO= 2.5 V, V_TRK = 0.6 V, MODE = VCC		1.2	1.5	mA
I_VOUT-SD	VOUT current in shutdown	V_UVLO= 0 V, V_OUT= 11.3 V			1	µA
I_VOUT-DS	VOUT current in deep sleep (diode emulation mode)	V_UVLO= 2.5 V, V_TRK = 0.25 V, V_OUT= 12 V		1.2	1.5	µA
I_VOUT-ACTIVE	VOUT current in active (non-switching)	V_UVLO= 2.5 V, V_TRK = 0.6 V, MODE = VCC		42	55	µA
I_BATTERY-SD	Battery drain in shutdown	V_UVLO= 0 V, V_OUT= 11.3 V		2.5	5	µA
I_BATTERY-DS1	Battery drain in deep sleep (skip or diode emulation mode, charge pump off)	V_UVLO= 2.5 V, V_TRK = 0.25 V, V_SYNC= 0 V		11	17	µA
I_BATTERY-DS2	Battery drain in deep sleep (FPWM mode, charge pump off)	V_UVLO= 2.5 V, V_TRK = 0.25 V, V_SYNC= 0 V		41	70	µA
I_BATTERY-DS3	Battery drain in deep sleep (skip or diode emulation mode, charge pump on)	V_UVLO= 2.5 V, V_TRK = 0.25 V, V_SYNC= 2.5 V		33	62	µA
I_BATTERY-DS4	Battery drain in deep sleep (FPWM mode, charge pump on)	V_UVLO= 2.5 V, V_TRK = 0.25 V, V_SYNC= 2.5 V		115	155	µA
ENABLE, UVLO
V_EN-RISING	Enable threshold	EN rising	0.45	0.55	0.65	V
V_EN-FALLING	Enable threshold	EN falling	0.35	0.45	0.55	V
V_EN-HYS	Enable hysteresis	EN falling	55	90	130	mV
I_UVLO-HYS	UVLO pulldown hysteresis current	V_UVLO = 0.7 V	8	10	12	µA
V_UVLO-RISING	UVLO threshold	UVLO rising	1.05	1.1	1.15	V
V_UVLO-FALLING	UVLO threshold	UVLO falling	1.025	1.075	1.125	V
V_UVLO-HYS	UVLO hysteresis	UVLO falling		25		mV
SYNC/DITHER/VH/CP
V_SYNC-RISING	SYNC threshold/SYNC detection threshold	SYNC rising			2	V
V_SYNC-FALLING	SYNC threshold	SYNC falling	0.4			V
	Minimum SYNC pull up pulse width				100	ns
I_DITHER	Dither source/sink current		16	21	26	µA
Δf_SW1	f_SW modulation (upper limit)			5%
Δf_SW2	f_SWmodulation (lower limit)			–6%
V_{DITHER-FALLING}	Dither disable threshold		0.65	0.75	0.85	V
VCC
V_VCC-REG1	VCC regulation	I_VCC= 100 mA	4.75	5	5.25	V
V_VCC-REG2	VCC regulation	No load	4.75	5	5.25	V
V_VCC-REG3	VCC regulation during dropout	V_BIAS= 3.8 V, I_VCC= 100 mA	3.45			V
V_{VCC-UVLO-RISING}	VCC UVLO threshold	VCC rising	3.55	3.65	3.75	V
V_{VCC-UVLO-FALLING}	VCC UVLO threshold	VCC falling	3.2	3.3	3.4	V
I_VCC-CL	VCC sourcing current limit	V_VCC = 4 V	100			mA
CONFIGURATION (MODE)
V_MODE-RISING	FPWM mode threshold	MODE rising			2.0	V
V_MODE-FALLING	Diode emulation mode threshold	MODE falling	0.4			V
RT
V_RT	RT regulation			0.5		V
VREF, TRK, VOUT
V_REF	VREF regulation target		0.99	1	1.005	V
V_OUT-REG	VOUT regulation target1 with resistor divider (lower VOUT range)	VREF resistor divider to make V_TRK = 0.25 V, R_VREF = 65 kΩ	4.915	5	5.085	V
V_OUT-REG	VOUT regulation target2 with resistor divider (lower VOUT range)	VREF resistor divider to make V_TRK = 0.5 V, R_VREF = 65 kΩ	9.9	10	10.1	V
V_OUT-REG	VOUT regulation target3 with resistor divider (lower VOUT range)	VREF resistor divider to make V_TRK = 1.0 V, R_VREF = 65 kΩ	19.8	20	20.2	V
V_OUT-REG	VOUT regulation target4 with resistor divider (upper VOUT range)	VREF resistor divider to make V_TRK = 0.25 V, R_VREF = 35 kΩ	14.74	15	15.24	V
V_OUT-REG	VOUT regulation target5 with resistor divider (upper VOUT range)	VREF resistor divider to make V_TRK = 0.5 V, R_VREF = 35 kΩ	29.7	30	30.3	V
V_OUT-REG	VOUT regulation target6 with resistor divider (upper VOUT range)	VREF resistor divider to make V_TRK = 0.95 V, R_VREF = 35 kΩ	56.43	57	57.57	V
V_OUT-REG	VOUT regulation target1 using TRK (lower VOUT range)	V_TRK = 0.25 V, R_VREF = 65 kΩ	4.91	5	5.09	V
V_OUT-REG	VOUT regulation target2 using TRK (lower VOUT range)	V_TRK = 0.5 V, R_VREF = 65 kΩ	9.88	10	10.11	V
V_OUT-REG	VOUT regulation target3 using TRK (lower VOUT range)	V_TRK = 1.0 V, R_VREF = 65 kΩ	19.8	20	20.2	V
V_OUT-REG	VOUT regulation target4 using TRK (upper VOUT range)	V_TRK = 0.25 V, R_VREF = 35 kΩ	14.71	15	15.25	V
V_OUT-REG	VOUT regulation target5 using TRK (upper VOUT range)	V_TRK = 0.5 V, R_VREF = 35 kΩ	29.6	30	30.3	V
V_OUT-REG	VOUT regulation target6 using TRK (upper VOUT range)	V_TRK = 0.95 V, R_VREF = 35 kΩ	56.45	57	57.5	V
I_TRK	TRK bias current				1	uA
SOFT START, DE to FPWM TRANSITION
I_SS	Soft-start current		17	20	23	µA
V_SS-DONE	MODE transition start	SS rising	1.3	1.5	1.7	V
R_SS	SS pulldown switch R_DSON			30	70	Ω
V_SS-DIS	SS discharge detection threshold		30	50	75	mV
V_SS-FB	Internal SS to FB clamp	V_FB = 0 V		55	75	mV
CURRENT SENSE (CSP, CSN, SW, SENSE)
V_SLOPE	Peak slope compensation amplitude	Referenced to CS input		45		mV
A_CS	Current sense amplifier gain	CSP = 3.0 V		10		V/V
	Current sense amplifier gain	CSP = 1.5 V		10		V/V
V_CLTH	Positive peak current limit threshold (CSP-CSN)	CSP = 3.0 V, MODE = GND	54	60	66	mV
	Positive peak current limit threshold (CSP-CSN)	CSP = 1.5 V, MODE = GND	51	60	72	mV
V_ZCD-DE	ZCD threshold (SW-SENSE)	MODE = GND		4		mV
I_CSN	CSN bias current				1	µA
I_CSP	CSP bias current			110		µA
BOOT FAULT PROTECTION (HB)
	Maximum replenish pulse cycles			4		cycles
	Replenish off cycles			12		cycles
	Number of sets to enter hiccup mode protection			4		sets
	Off-cycle during hiccup mode off			512		cycles
ERROR AMPLIFIER (COMP)
Gm	Transconductance			1		mA/V
I_SOURCE-MAX	Maximum COMP sourcing current	V_COMP = 0 V	95			µA
I_SINK-MAX	Maximum COMP sinking current	V_COMP = 1.8 V	90			µA
V_CLAMP-MAX	COMP maximum clamp voltage	COMP rising	1.8	2.2	2.55	V
V_CLAMP-MIN	COMP minimum clamp voltage, active in sleep and deep sleep mode	COMP falling		0.25		V
PULSE WIDTH MODULATION (PWM)
f_SW1	Switching frequency	R_T = 220 kΩ	85	100	115	kHz
f_SW2	Switching frequency	R_T = 9.09 kΩ	1980	2200	2420	kHz
t_ON-MIN	Minimum controllable on-time	R_T = 9.09 kΩ	14	20	50	ns
t_OFF-MIN	Minimum forced off-time	R_T = 9.09 kΩ	70	95	115	ns
D_MAX1	Maximum duty cycle limit	R_T = 220 kΩ	90%	94%	98%
D_MAX2	Maximum duty cycle limit	R_T = 9.09 kΩ	75%	80%	83%
LOW IQ SLEEP MODE
V_WAKE	Internal wakeup threshold	VOUT falling (referenced to V_OUT-REG)		98.5%
	Sleep to wake-up delay	R_T = 9.09 kΩ		5		μs
PGOOD, OVP
V_OVTH-RISING	Overvoltage threshold (OVP threshold)	VOUT rising (reference to V_OUT-REG)	104.5%	108%	111%
V_OVTH-FALLING	Overvoltage threshold (OVP threshold)	VOUT falling (reference to V_OUT-REG)	100.5%	105%	109%
V_UVTH-RISING	Undervoltage threshold (PGOOD threshold)	VOUT rising (reference to V_OUT-REG)	91.5%	94%	98%
V_UVTH-FALLING	Undervoltage threshold (PGOOD threshold)	VOUT falling (reference to V_OUT-REG)	89.5%	92%	95.5%
	UV comparator deglich filter	Rising edge		26		µs
	UV comparator deglich filter	Falling edge		21		µs
R_PGOOD	PGOOD pulldown switch R_DSON			90	180	Ω
	Minimum BIAS for valid PGOOD				2.5	V
MOSFET DRIVER
	High-state voltage drop (HO driver)	100-mA sinking		0.08	0.15	V
	Low-state voltage drop (HO driver)	100-mA sourcing		0.04	0.1	V
	High-state voltage drop (LO driver)	100-mA sinking		0.08	0.17	V
	Low-state voltage drop (LO driver)	100-mA sourcing		0.04	0.1	V
V_HB-UVLO	HB-SW UVLO threshold	HB-SW falling	2.2	2.5	3.0	V
I_HB-SLEEP	HB quiescent current in sleep	HB-SW = 5V		3.5	7	µA
t_DHL	HO off to LO on deadtime			20		ns
t_DLH	LO off to HO on deadtime			22		ns
	HB diode resistance			1.2		Ω
THERMAL SHUTDOWN
T_TSD-RISING	Thermal shutdown threshold	Temperature rising		175		°C
T_TSD-HYS	Thermal shutdown hysteresis			15		°C

7.6 Typical Characteristics

Figure 7-1 Frequency vs RT Resistance

Figure 7-3 Frequency vs Temperature
(RT = 220 kΩ, 100 kHz)

Figure 7-5 V_BIAS vs I_BIAS (Bypass Mode, Charge Pump On)

Figure 7-7 V_BIAS vs I_BIAS (Shutdown Mode)

Figure 7-9 V_VCC vs I_VCC

Figure 7-11 Peak Current Limit Threshold vs V_CSP

Figure 7-13 I_CSP vs Temperature (Active Mode)

Figure 7-15 V_OUT Sink Current vs Temperature (Deep Sleep)

Figure 7-17 D_MAX vs Frequency

Figure 7-2 Frequency vs Temperature
(RT = 9.09 kΩ, 2.2 MHz)

Figure 7-4 V_BIAS vs I_BIAS (Active Mode)

Figure 7-6 V_BIAS vs I_BIAS (Bypass Mode, Charge Pump Off)

Figure 7-8 V_BIAS vs V_VCC

Figure 7-10 V_VCC vs Peak Driver Current

Figure 7-12 Peak Current Limit Threshold V_CLTH vs Temperature (CSP = 3 V)

Figure 7-14 VOUT Sink Current vs VOUT (Deep Sleep)

Figure 7-16 V_REF vs Temperature

8 Detailed Description

8.1 Overview

The LM5123-Q1 device is a wide input range synchronous boost controller that employs peak current mode control. The device features a low shutdown I_Q and a low I_Q sleep mode, which minimizes battery drain at no/light load condition. The device also supports an ultra-low I_Q deep sleep mode with bypass operation, which eliminates the need for an external bypass switch when the supply voltage is greater than the boost output regulation target. The output voltage can be dynamically programmed by using the tracking function.

The wide input range of the device supports automotive cold-crank and load dump. The minimum input voltage can be as low as 0.8 V when BIAS is equal to or greater than 3.8 V. The switching frequency is dynamically programmed with an external resistor from 100 kHz to 2.2 MHz. Switching at 2.2 MHz minimizes AM band interference and allows for a small solution size and fast transient response. Controller architecture simplifies thermal management at harsh ambient temperature conditions when compared to converter architectures.

The device has built-in protection features such as peak current limit, which is constant over VIN, overvoltage protection, and thermal shutdown. External clock synchronization, programmable spread spectrum modulation, and a lead-less package with minimal parasitic, help reduce EMI and avoid cross talk. Additional features include the following:

Line UVLO
FPWM
Diode emulation
DCR inductor current sensing
Programmable soft start
Power-good indicator

8.2 Functional Block Diagram

8.3 Feature Description

Note:

Read through Section 8.4 before reading the feature description of the device. It is recommended to understand which device functional modes and what type of light load switching modes are supported by the device.

The parameters or thresholds values mentioned in this section are reference values unless otherwise specified. Refer to the Electrical Characteristics to find the minimum, maximum, and typical values.

8.3.1 Device Enable/Disable (EN, VH Pin)

The device shuts down when EN is less than the EN threshold (V_EN) and VH is less than the SYNC threshold (V_SYNC). The device is enabled when EN is greater than V_EN or VH is greater than V_SYNC. The VH pin provides a 40-μs internal delay before the device shuts down.

During shutdown a 33-kΩ internal pulldown resistor on the EN pin is connected to GND to prevent a false turn-on when the pin is floating. Once EN goes above the EN threshold (V_EN), the 33-kΩ resistor is disconnected and the I_UVLO-HYS current source is enabled to provide the UVLO functionality. The I_UVLO-HYS current is designed to avoid chatter around the EN threshold voltage.

Figure 8-1 EN/UVLO Circuit

8.3.2 High Voltage VCC Regulator (BIAS, VCC Pin)

The device features a high voltage 5-V VCC regulator, which is sourced from the BIAS pin. The internal VCC regulator turns on 50 μs after the device is enabled, and 120-μs device configuration starts when VCC is above VCC UVLO threshold (V_VCC-UVLO). The device configuration is reset when the device shuts down or VCC falls down below 2.2 V. The preferred way to reconfigure the device is to shut down the device. During configuration time, the light load switching mode and VOUT range are selected.

The high voltage VCC regulator allows the connection of the BIAS pin directly to supply voltages from 3.8 V to 42 V. When BIAS is less than the 5-V VCC regulation target (V_VCC-REG), the VCC output tracks the BIAS pin voltage with a small dropout voltage which is caused by 1.7-Ω resistance of the VCC regulator.

The recommended VCC capacitor value is 4.7 μF. The VCC capacitor should be populated between VCC and PGND as close to the device. The recommended BIAS capacitor value is 1.0 μF. The BIAS capacitor must be populated between BIAS and PGND close to the device.

Figure 8-2 High Voltage VCC Regulator

The VCC regulator features a VCC current limit function that prevents device damage when the VCC pin is shorted to ground accidentally. The minimum sourcing capability of the VCC regulator is 100 mA (I_VCC-CL) during either the device configuration time or active mode operation. The minimum sourcing capability of the VCC regulator is reduced to 1 mA during sleep mode or deep sleep mode, or when EN is less than V_EN and VH is greater than V_SYNC. The VCC regulator supplies the internal drivers and other internal circuits. The external MOSFETs must be carefully selected to make the driver current consumption less than I_VCC-CL. The driver current consumption can be calculated in Equation 1.

Equation 1. I_G = 2 × Q_G@5V × f_SW

where

Q_G@5V is the N-channel MOSFET gate charge at 5 V gate-source voltage.

If VIN operation below 3.8 V is required, the BIAS pin must be connected to the output of the boost converter (V_LOAD). By connecting the BIAS pin to V_LOAD, the boost converter input voltage (V_SUPPLY) can drop down to 0.8 V if BIAS is greater than 3.8 V. See Section 8.3.17 for more detailed information about the minimum V_SUPPLY.

8.3.3 Light Load Switching Mode Selection (MODE Pin)

The light load switching mode is selected during the device configuration. The device is configured to skip mode when the MODE pin is floating or a resistor that is greater than 500 kΩ is connected between MODE and AGND during the device configuration. Once the device is configured to skip mode, the light load switching mode cannot be changed until reconfiguring the device.

If the MODE pin voltage is less than 0.4 V (V_MODE-FALLING) or grounded during the device configuration, the device is configured to diode emulation (DE) mode. If the MODE pin voltage is greater than 2.0 V (V_MODE-RISING) or connected to VCC during the device configuration, the device is configured to forced PWM (FPWM) mode. If the device is configured to DE or FPWM mode, the light load switching mode can be dynamically changed between DE and FPWM modes during operation without reconfiguration.

Figure 8-3 MODE Selection Circuit

8.3.4 V_OUT Range Selection (RANGE Pin)

The programmable V_OUT range is selected during the device configuration and it cannot be changed until the user reconfigures the device. Lower V_OUT range (5 V to 20 V) is selected if the resistance from VREF to AGND (R_VREFT + R_VREFB) is in the range of 75 kΩ to 100 kΩ during the device configuration. Upper V_OUT range (15 V to 57 V) is selected if the resistance from VREF to AGND is in the range of 20 kΩ to 35 kΩ during the device configuration. The accuracy of the V_OUT regulation is specified within the selected range.

8.3.5 Line Undervoltage Lockout (UVLO Pin)

When UVLO is greater than the UVLO threshold (V_UVLO), the device enters active mode if the device configuration is finished. UVLO hysteresis is accomplished with an internal 25-mV voltage hysteresis (V_UVLO-HYS) at the UVLO pin, and an additional 10-μA current sink (I_UVLO-HYS) that is switched on or off. When the UVLO pin voltage exceeds V_UVLO, the current sink is disabled to quickly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below V_UVLO or during the device configuration time, the current sink is enabled, causing the voltage at the UVLO pin to fall quickly.

The external UVLO resistor voltage divider (R_UVLOT, R_UVLOB) must be designed so that the voltage at the UVLO pin is greater than V_UVLO when V_SUPPLY is in the desired operating range. The values of R_UVLOT and R_UVLOB can be calculated as follows.

Equation 2.

$R_{U V L O T} = \frac{(V_{S U P P L Y_O N} - \frac{V_{U V L O_R I S I N G}}{V_{U V L O_F A L L I N G}} \times V_{S U P P L Y_O F F})}{I_{U V L O_H Y S}}$

Equation 3.

$R_{U V L O B} = \frac{V_{U V L O_F A L L I N G} \times R_{U V L O T}}{V_{S U P P L Y_O F F} - V_{U V L O_F A L L I N G}}$

A UVLO capacitor (C_UVLO) is required in case V_SUPPLY drops below V_SUPPLY-OFF momentarily during the start-up or during a severe load transient at the low input voltage. If the required UVLO capacitor is large, an additional series UVLO resistor (R_UVLOS) can be used to quickly raise the voltage at the UVLO pin when I_UVLO-HYS is disabled.

The UVLO pin can be connected to the BIAS pin if not used. Drive the UVLO pin through a minimum of a 5-kΩ resistor if the BIAS pin voltage is less than the UVLO pin voltage in any conditions.

8.3.6 Fast Restart using VCC HOLD (VH Pin)

The device is prepared for a fast start or restart when VH is greater than V_SYNC. The device configuration is done and the VCC regulator is active. The device stops switching, but keeps the VCC regulator active when EN is less than V_EN and VH is greater than V_SYNC (see Figure 8-5).

Figure 8-4 Boost Start-Up Waveforms Case 1: Start-Up by EN/UVLO, Restart when VH < V_SYNC

Figure 8-5 Boost Start-Up Waveforms Case 2: Start-Up by EN/UVLO, Restart when VH > V_SYNC

8.3.7 Adjustable Output Regulation Target (VOUT, TRK, VREF Pin)

The V_OUT regulation target (V_OUT-REG) is adjustable by programming the TRK pin voltage, which is the reference of the internal error amplifier. The accuracy of V_OUT-REG is given when the TRK voltage is between 0.25 V and 1.0 V. The high impedance TRK pin allows users to program the pin voltage directly by a D/A converter or by connecting to a resistor voltage divider (R_VREFT, R_VREFB) between VREF and AGND.

The device provides a 1-V voltage reference (V_REF), which can be used to program the TRK pin voltage through a resistor voltage divider. It is not recommended to use V_REF as a reference voltage of an external circuit because the device periodically disables V_REF in sleep or deep sleep mode. For stability reasons, the VREF capacitor (C_VREF) should be between 330 pF and 1 nF. 470 pF is recommended.

When R_VREFT and R_VREFB are used to program the TRK pin voltage, V_OUT-REG can be calculated as follows.

Lower V_OUT Range

Equation 4. $V_{O U T_R E G} = \frac{20 \times R_{V R E F B}}{R_{V R E F B} + R_{V R E F T}}$

Upper V_OUT Range

Equation 5. $V_{O U T_R E G} = \frac{60 \times R_{V R E F B}}{R_{V R E F B} + R_{V R E F T}}$

The TRK pin voltage can be dynamically programmed in active mode, which makes an envelope tracking power supply design easy. When designing a tracking power supply, it is required to adjust the TRK pin voltage slow enough so that the VOUT pin voltage can track the command and the internal overvoltage or undervoltage comparator is not triggered during the transient operation. An RC filter must be used at the TRK pin to slow down the slew rate of the command signal at the TRK pin, especially when a step input is applied. When a trapezoidal or sinusoidal input is applied, the slew rate or the frequency of the command signal must be limited.

Figure 8-6 TRK Control (a) using VREF (b) by External Step Input

In FPWM operation, V_OUT-REG tracks the TRK pin voltage immediately as well during deep sleep mode. While in skip or diode mode operation, V_OUT-REG tracks the TRK pin voltage pin voltage with a maximum of a 20 ms delay during deep sleep mode to save power. Take extra care when programming TRK if V_SUPPLY is greater than V_OUT-REG in any conditions. The device enters active mode with a 5-μs delay if V_LOAD falls down below V_OUT-REG in deep sleep mode, but the device enters active mode with maximum of a 20 ms delay if V_OUT-REG is increased by TRK above V_LOAD in deep sleep mode.

8.3.8 Overvoltage Protection (VOUT Pin)

The device provides an overvoltage protection (OVP) for boost converter output. The OVP comparator monitors the VOUT pin through an internal resistor voltage resistors. If the VOUT pin voltage rises above the overvoltage threshold (V_OVTH), OVP is activated. When OVP is triggered, the device turns off the low-side driver and turns on the high-side driver until zero current is detected in diode emulation or skip mode. In FPWM mode, the low-side driver is not turned off when the OVP is triggered.

After at least 40 μs in OVP status, the device enters deep sleep mode and turns on the high-side driver 100%. The recommended VOUT capacitor (C_VOUT) is 0.1 μF.

8.3.9 Power Good Indicator (PGOOD Pin)

The device provides a power-good indicator (PGOOD) to simplify sequencing and supervision. PGOOD is an open-drain output and a pullup resistor between 5 kΩ and 100 kΩ can be externally connected. The PGOOD switch opens when the VOUT pin voltage is greater than the undervoltage threshold (V_UVTH). The PGOOD pin is pulled down to ground when the VOUT pin voltage is less than V_UVTH, UVLO is less than V_UVLO, VCC is less than V_VCC-UVLO, or during thermal shutdown. A 26-μs rising and 21-μs falling deglitch filter prevents any false pulldown of the PGOOD due to transients. The PGOOD pin voltage cannot be greater than V_VOUT + 0.3 V.

Figure 8-7 PGOOD Indicator