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  • DACx1001 20 位、18 位和 16 位的低噪声、超低谐波失真、快速趋稳、高电压输出数模转换器 (DAC)

    • ZHCSKD4A October   2019  – December 2019 DAC11001A , DAC81001 , DAC91001

      UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

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  • DACx1001 20 位、18 位和 16 位的低噪声、超低谐波失真、快速趋稳、高电压输出数模转换器 (DAC)
  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      功能方框图
      2.      高精度控制环路电路
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1      Absolute Maximum Ratings
    2. 7.2      ESD Ratings
    3. 7.3      Recommended Operating Conditions
    4. 7.4      Thermal Information Package
    5. 7.5      Electrical Characteristics
    6. Table 1. Timing Requirements: Write, 4.5 V ≤ DVDD ≤ 5.5 V
    7. Table 2. Timing Requirements: Write, 2.7 V ≤ DVDD < 4.5 V
    8. Table 3. Timing Requirements: Read and Daisy-Chain Write, 4.5 V ≤ DVDD ≤ 5.5 V
    9. Table 4. Timing Requirements: Read and Daisy-Chain Write, 2.7 V ≤ DVDD < 4.5 V
    10. 7.6      Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital-to-Analog Converter Architecture
      2. 8.3.2 External Reference
      3. 8.3.3 Output Buffers
      4. 8.3.4 Internal Power-On Reset (POR)
      5. 8.3.5 Temperature Drift and Calibration
      6. 8.3.6 DAC Output Deglitch Circuit
    4. 8.4 Device Functional Modes
      1. 8.4.1 Fast-Settling Mode and THD
      2. 8.4.2 DAC Update Rate Mode
    5. 8.5 Programming
      1. 8.5.1 Daisy-Chain Operation
      2. 8.5.2 CLR Pin Functionality and Software Clear
      3. 8.5.3 Output Update (Synchronous and Asynchronous)
        1. 8.5.3.1 Synchronous Update
        2. 8.5.3.2 Asynchronous Update
      4. 8.5.4 Software Reset Mode
    6. 8.6 Register Map
      1. 8.6.1 NOP Register (address = 00h) [reset = 0x000000h]
        1. Table 9. NOP Register Field Descriptions
      2. 8.6.2 DAC-DATA Register (address = 01h) [reset = 0x000000h]
        1. Table 10. DAC-DATA Register Field Descriptions
      3. 8.6.3 CONFIG1 Register (address = 02h) [reset = 004C80h for bits [23:0]]
        1. Table 11. CONFIG1 Register Field Descriptions
      4. 8.6.4 DAC-CLEAR-DATA Register (address = 03h) [reset = 000000h for bits [23:0]]
        1. Table 12. DAC-CLEAR-DATA Register Field Descriptions
      5. 8.6.5 TRIGGER Register (address = 04h) [reset = 000000h for bits [23:0]]
        1. Table 13. TRIGGER Register Field Descriptions
      6. 8.6.6 STATUS Register (address = 05h) [reset = 000000h for bits [23:0]]
        1. Table 14. STATUS Register Field Descriptions
      7. 8.6.7 CONFIG2 Register (address = 06h) [reset = 000040h for bits [23:0]]
        1. Table 15. CONFIG2 Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Source Measure Unit (SMU)
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Battery Test Equipment (BTE)
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 High-Precision Control Loop
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
      4. 9.2.4 Arbitrary Waveform Generation (AWG)
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
        3. 9.2.4.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Interfacing to a Processor
      2. 9.3.2 Interfacing to a Low-Jitter LDAC Source
      3. 9.3.3 Embedded Resistor Configurations
        1. 9.3.3.1 Minimizing Bias Current Mismatch
        2. 9.3.3.2 2x Gain configuration
        3. 9.3.3.3 Generating Negative Reference
    4. 9.4 What to Do and What Not to Do
      1. 9.4.1 What to Do
      2. 9.4.2 What Not to Do
    5. 9.5 Initialization Set Up
  10. 10Power Supply Recommendations
    1. 10.1 Power-Supply Sequencing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 开发支持
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 相关链接
    4. 12.4 接收文档更新通知
    5. 12.5 支持资源
    6. 12.6 商标
    7. 12.7 静电放电警告
    8. 12.8 Glossary
  13. 13机械、封装和可订购信息
  14. 重要声明
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DATA SHEET

DACx1001 20 位、18 位和 16 位的低噪声、超低谐波失真、快速趋稳、高电压输出数模转换器 (DAC)

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 20 位单调性：1-LSB DNL（最大值）
  • 积分线性：4-LSB INL（最大值）
  • 低噪声：7nV/√Hz
  • 独立于代码的低干扰：
    1nV-s
  • 出色的 THD：1kHz fOUT 时为 -105 dB
  • 快速趋稳：1µs
  • 灵活的输出范围：VREFPF 至 VREFNF
  • 集成式精密反馈电阻器
  • 50MHz、4 线 SPI 兼容接口
    • 读回
    • 菊花链
  • 温度范围：-40°C 至 +125°C
  • 封装：48 引脚 TQFP

2 应用

  • 实验室和现场仪表
  • 光谱仪
  • 模拟输出模块
  • 电池测试
  • 半导体测试
  • 任意波形发生器 (AWG)
  • MRI
  • X 射线系统
  • 专业音频放大器（机架式）

3 说明

20 位 DAC11001A、18 位 DAC91001 和 16 位 DAC81001 (DACx1001) 是高精度、低噪声、电压输出、单通道数模转换器 (DAC)。DACx1001 根据设计具有单调性，可以在所有范围内提供低于 4LSB（最大值）的出色线性度。

非缓冲电压输出可提供低噪声性能 (7nV/√Hz) 和快速稳定时间 (1µs)，因此这款器件非常适合低噪声、快速控制环路和波形生成 应用中的数字输入 D 类音频放大器。DACx1001 兼具增强型抗尖峰脉冲电路以及独立于代码的超低干扰 (1nV-s)，可实现干净的波形斜升和超低总谐波失真 (THD)。

DACx1001 器件包含上电复位电路，因此 DAC 能够使用寄存器中的已知值供电。使用外部基准，可以实现 VREFPF 到 VREFNF 的 DAC 输出，包括非对称输出范围。

DACx1001 使用一个在高达 50MHz 的时钟频率下运行的通用 4 线串行接口。DACx1001 的额定工业工作温度范围为 -40°C 至 +125°C。

器件信息(1)

器件型号 封装 封装尺寸（标称值）
DAC11001 TQFP (48) 7.00mm × 7.00mm
DAC91001（预发布）
DAC81001（预发布）
  1. 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。

Device Images

功能方框图

DAC11001A DAC91001 DAC81001 SLASEL0_Block_Dia.gif

高精度控制环路电路

DAC11001A DAC91001 DAC81001 dac11001-closed-loop-control.gif

4 修订历史记录

Changes from * Revision (October 2019) to A Revision

  • Changed 将 DAC11001A 器件从“预告信息（预发布）”更改为“生产数据（正在供货）”Go

5 Device Comparison Table

DEVICE RESOLUTION
DAC11001A 20-bit
DAC91001 (preview) 18-bit
DAC81001 (preview) 16-bit

6 Pin Configuration and Functions

PFB Package
48-Pin TQFP
Top View

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
AGND 2, 35, 38, 40, 42, 43, 46, 47 Analog ground Connect to 0 V.
AGND-OUT 8 Analog ground Connect to 0 V. Measure DAC output voltage with respect to this node.
AGND-TnH 14 Analog ground Connect to 0 V. Integrated deglitcher clock ground..
ALARM 19 Output Alarm output
AVDD 39, 41 Power Positive low voltage analog power supply
CLR 30 Input DAC registers clear pin, active low
DGND 16, 17, 20, 21, 22, 23, 26 Digital ground Connect to 0 V.
DVDD 27 Power Digital power supply pin
RFB 9 Input Integrated precision resistor feedback node
IOVDD 28 Power Interface power supply pin
LDAC 18 Input Load DAC pin, active low
NC 1, 12, 13, 15, 24, 25, 29, 36, 37, 48 — No connection, leave floating
OUT 7 Output Unbuffered voltage output
RCM 11 Input Integrated precision resistor common-mode node
REFNF 5 Input External negative reference input. Connect to 0 V for unipolar DAC output.
REFNS 6 Input External negative reference sense node
REFPF 3 Input External positive reference input
REFPS 4 Input External positive reference sense node
ROFS 10 Input Integrated precision resistor offset node
SCLK 31 Input Serial clock input of serial peripheral interface (SPI). Schmitt-trigger logic input.
Data are transferred at rates of up to 50 MHz.
SDIN 32 Input Serial data input. Schmitt-trigger logic input.
Data are clocked into the input shift register on the falling edge of the serial clock input.
SDO 34 Output Serial data output. Data are valid on the falling edge of SCLK.
SYNC 33 Input SPI bus chip select input (active low). Data bits are not clocked into the serial shift register unless SYNC is low. When SYNC is high, the SDO pin is in high-impedance status.
VCC 45 Power Analog positive power supply
VSS 44 Power Analog negative power supply

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Positive supply voltage AVDD to AGND –0.3 7 V
VCC to VSS –0.3 40
VCC to AGND –0.3 40
Negative supply voltage VSS to AGND –19 0.3 V
Positive reference voltage VREFPF to VREFNF –0.3 40 V
VREFPF to VCC –0.3 VCC + 0.3
VREFPF to AGND –0.3 40
Negative reference voltage VREFNF to AGND –19 0.3 V
VREFNF to VSS VSS – 0.3 0.3
Digital and IO power supply DVDD, IOVDD to DGND –0.3 7 V
Digital input(s) to DGND DGND – 0.3 IOVDD + 0.3 V
VOUT, VRFB, VRCM, VROFS to AGND (VSS = AGND) VSS VCC V
to VSS 0 VCC
Alarm pin voltage, ALARM to DGND –0.3 DVDD + 0.3 V
Digital output, SDO to DGND –0.3 DVDD + 0.3 V
Current into any pin –10 10 mA
TJ Junction temperature 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

 
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