具有内部 EEPROM 的 LMK61E2 超低抖动可编程振荡器

8.3.1 Device Block-Level Description

The LMK61E2 comprises of an integrated oscillator that includes a 50-MHz crystal, a fractional PLL with integrated VCO that supports a frequency range of 4.6 GHz to 5.6 GHz. The PLL block consists of a phase frequency detector (PFD), charge pump, integrated passive loop filter, a feedback divider that can support both integer and fractional values and a delta-sigma engine for noise suppression in fractional PLL mode. Completing the device is the combination of an integer output divider and a universal differential output buffer. The PLL is powered by on-chip low dropout (LDO) linear voltage regulators and the regulated supply network is partitioned such that the sensitive analog supplies are running from separate LDOs than the digital supplies which use their own LDO. The LDOs provide isolation to the PLL from any noise in the external power supply rail with a PSRR of better than –70 dBc at 50-kHz to 1-MHz ripple frequencies at 3.3-V device supply. The device supports fine and coarse frequency margining by changing the settings of the integrated oscillator and the output divider respectively.

8.3.2 Device Configuration Control

The LMK61E2 supports I²C programming interface where an I²C host can update any device configuration after the device enables the host interface and the host writes a sequence that updates the device registers. Once the device configuration is set, the host can also write to the on-chip EEPROM for a new set of power-up defaults based on the configuration pin settings in the soft pin configuration mode.

8.3.3 Register File Reference Convention

Figure 24 shows the method that this document employs to refer to an individual register bit or a grouping of register bits. If a drawing or text references an individual bit the format is to specify the register number first and the bit number second. The LMK61E2 contains 38 registers that are 8 bits wide. The register addresses and the bit positions both begin with the number zero (0). A period separates the register address and bit address. The first bit in the register file is address ‘R0.0’ meaning that it is located in Register 0 and is bit position 0. The last bit in the register file is address ‘R72.7’ referring to the 8th bit of register address 72 (the 73rd register in the device). Figure 24 also lists specific bit positions as a number contained within a box. A box with the register address encloses the group of boxes that represent the bits relevant to the specific device circuitry in context.

Figure 24. LMK61E2 Register Reference Format

8.3.4 Configuring the PLL

The PLL in LMK61E2 can be configured to accommodate various output frequencies either through I²C programming interface or in the absence of programming, the PLL defaults stored in EEPROM is loaded on power up. The PLL can be configured by setting the Reference Doubler, Integrated PLL Loop Filter, Feedback Divider, and Output Divider.

For the PLL to operate in closed-loop mode, the following condition in Equation 1 has to be met.

The output frequency is related to the VCO frequency as given in Equation 2.

8.3.5 Integrated Oscillator

The integrated oscillator in LMK61E2 features programmable load capacitances that can be set to either operate at exactly its nominal oscillation frequency or operate at a fixed frequency offset from its nominal oscillation frequency. This is done by programming R16 and R17. More details on frequency margining are provided in Fine Frequency Margining.

8.3.6 Reference Doubler

The reference path has a frequency doubler that can be enabled by programming R34.5 = 1. Enabling the doubler allows a higher comparison frequency for the PLL and would result in a 3-dB reduction in the in-band phase noise at the output of the LMK61E2. Enabling the doubler also results in higher reference and phase detector spurs which will be minimized by enabling the higher order components (R3, C3) of the loop filter and programmed to appropriate values. Disabling the doubler would result in higher in-band phase noise on the device output than when the doubler is enabled but the reference and phase detector spurs would be lower on the device output than when the doubler is enabled.

8.3.7 Phase Frequency Detector

The Phase Frequency Detector (PFD) of the PLL takes inputs from the reference path and the feedback divider output and produces an output that is dependent on the phase and frequency difference between the two inputs. The input frequency of the PFD is 50 MHz when reference doubler is disabled, or 100 MHz when reference doubler is enabled.

8.3.8 Feedback Divider (N)

The N divider of the PLL includes fractional compensation and can achieve any fractional denominator (DEN) from 1 to 4,194,303. The integer portion, INT, is the whole part of the N divider value and the fractional portion, NUM / DEN, is the remaining fraction. INT, NUM, and DEN are programmed in R25, R26, R27, R28, R29, R30, R31, and R32. The total programmed N divider value, N, is determined by: N = INT + NUM / DEN. The output of the N divider sets the PFD frequency to the PLL and should equal 50 MHz, when reference doubler is disabled, or 100 MHz, when reference doubler is enabled.

8.3.9 Fractional Circuitry

The delta signal modulator is a key component of the fractional circuitry and is involved in noise shaping for better phase noise and spurs in the band of interest. The order of the delta sigma modulator is selectable between integer mode and third order, for fractional PLL mode, and can be programmed in R33[1-0]. Dithering can be programmed in R33[3-2] and should be disabled for integer PLL mode and set to weak for fractional PLL mode.

8.3.10 Charge Pump

The PLL has charge pump slices of 1.6 mA, to be used when PLL is set to fractional mode, or 6.4 mA, to be used when PLL is set to integer mode. These slices can be selected by programming R34[3-0]. When PLL is set to fractional mode, a phase shift needs to be introduced to maintain a linear response and ensure consistent performance across operating conditions and a value of 0x2 should be programmed in R35[6-4]. When PLL is set to integer mode, a value of 0x0 should be programmed in R35[6-4].

8.3.11 Loop Filter

The LMK61E2 features a fully integrated loop filter for the PLL and supports programmable loop bandwidth from 100 kHz to 1 MHz. The loop filter components, R2, C1, R3, and C3 can be configured by programming R36, R37, R38, and R39 respectively. The LMK61E2 features a fixed value of C2 of 10 nF. When PLL is configured in the fractional mode, R35.2 should be set to 1. When reference doubler is disabled for integer mode PLL, R35.2 should be set to 0 and R38[6-0] should be set to 0x00. When reference doubler is enabled for integer mode PLL, R35.2 should be set to 1 and R38 and R39 are written with the appropriate values. Figure 25 shows the loop filter structure of the PLL. It is important to set the PLL to best possible bandwidth to minimize output jitter. TI provides the WEBENCH® Clock Architect Tool that makes it easy to select the right loop filter components.

Figure 25. Loop Filter Structure of PLL

8.3.12 VCO Calibration

The PLL in LMK61E2 is made of LC VCO that is designed using high-Q monolithic inductors to oscillate between 4.6 GHz and 5.6 GHz and has low-phase noise characteristics. The VCO must be calibrated to ensure that the clock outputs deliver optimal phase noise performance. Fundamentally, a VCO calibration establishes an optimal operating point within the tuning range of the VCO. Setting R72.1 to 1 causes a VCO recalibration and is necessary after device reconfiguration. VCO calibration automatically occurs on device power up.

8.3.13 High-Speed Output Divider

The high-speed output divider supports divide values of 5 to 511 and are programmed in R22 and R23. The output divider also supports coarse frequency margining that can initiate as low as a 5% change in the output frequency.

8.3.14 High-Speed Clock Output

The clock output can be configured as LVPECL, LVDS, or HCSL by programming R21[1-0]. Interfacing to LVPECL, LVDS, or HCSL receivers are done either with direct coupling or with AC-coupling capacitor as shown in Figure 16 – Figure 21.

The LVDS output structure has integrated 125-Ω termination between each side (P and N) of the differential pair. The HCSL output structure is open drain and can be DC or AC coupled to HCSL receivers with appropriate termination scheme. The LVPECL output structure is an emitter follower requiring external termination.

8.3.15 Device Status

The PLL loss of lock and PLL calibration status can be monitored by reading R66[1-0]. These bits represent a logic-high interrupt output and are self-cleared once the readback is complete.

8.4.1 Interface and Control

The host (DSP, Microcontroller, FPGA, and so forth) configures and monitors the LMK61E2 through the I²C port. The host reads and writes to a collection of control and status bits called the register map. The device blocks can be controlled and monitored through a specific grouping of bits located within the register file. The host controls and monitors certain device Wide critical parameters directly through register control and status bits. In the absence of the host, the LMK61E2 can be configured to operate from its on-chip EEPROM. The EEPROM array is automatically copied to the device registers upon power up. The user has the flexibility to rewrite the contents of EEPROM from the SRAM up to a 100 times.

Within the device registers, there are certain bits that have read or write access. Other bits are read-only (an attempt to write to a read-only bit does not change the state of the bit). Certain device registers and bits are reserved, meaning that they must not be changed from their default reset state. Figure 26 shows interface and control blocks within LMK61E2 and the arrows refer to read access from and write access to the different embedded memories (EEPROM, SRAM).

Figure 26. LMK61E2 Interface and Control Block

8.5.1 I²C Serial Interface

The I²C port on the LMK61E2 works as a slave device and supports both the 100-kHz standard mode and 400-kHz fast mode operations. Fast mode imposes a glitch tolerance requirement on the control signals. Therefore, the input receivers ignore pulses of less than 50 ns duration. The I²C timing is given in I2C-Compatible Interface Characteristics (SDA, SCL). The timing diagram is given in Figure 27.

Figure 27. I²C Timing Diagram

In an I²C bus system, the LMK61E2 acts as a slave device and is connected to the serial bus (data bus SDA and lock bus SCL). These are accessed via a 7-bit slave address transmitted as part of an I²C packet. Only the device with a matching slave address responds to subsequent I²C commands. In soft pin mode, the LMK61E2 allows up to three unique slave devices to occupy the I²C bus based on the pin strapping of ADD (tied to VDD, GND, or left open). The device slave address is 10110xx (the two LSBs are determined by the ADD pin).

During the data transfer through the I²C interface, one clock pulse is generated for each data bit transferred. The data on the SDA line must be stable during the high period of the clock. The high or low state of the data line can change only when the clock signal on the SCL line is low. The start data transfer condition is characterized by a high-to-low transition on the SDA line while SCL is high. The stop data transfer condition is characterized by a low-to-high transition on the SDA line while SCL is high. The start and stop conditions are always initiated by the master. Every byte on the SDA line must be eight bits long. Each byte must be followed by an acknowledge bit and bytes are sent MSB first. The I²C register structure of the LMK61E2 is shown in Figure 28.

Figure 28. I²C Register Structure

The acknowledge bit (A) or non-acknowledge bit (A’) is the 9th bit attached to any 8-bit data byte and is always generated by the receiver to inform the transmitter that the byte has been received (when A = 0) or not (when A’ = 0). A = 0 is done by pulling the SDA line low during the 9th clock pulse and A’ = 0 is done by leaving the SDA line high during the 9th clock pulse.

The I²C master initiates the data transfer by asserting a start condition which initiates a response from all slave devices connected to the serial bus. Based on the 8-bit address byte sent by the master over the SDA line (consisting of the 7-bit slave address (MSB first) and an R/W’ bit), the device whose address corresponds to the transmitted address responds by sending an acknowledge bit. All other devices on the bus remain idle while the selected device waits for data transfer with the master.

After the data transfer has occurred, stop conditions are established. In write mode, the master asserts a stop condition to end data transfer during the 10th clock pulse following the acknowledge bit for the last data byte from the slave. In read mode, the master receives the last data byte from the slave but does not pull SDA low during the 9th clock pulse. This is known as a non-acknowledge bit. By receiving the non-acknowledge bit, the slave knows the data transfer is finished and enters the idle mode. The master then takes the data line low during the low period before the 10th clock pulse, and high during the 10th clock pulse to assert a stop condition. A generic transaction is shown in Figure 29.

Figure 29. Generic Programming Sequence

The LMK61E2 I²C interface supports Block Register Write/Read, Read/Write SRAM, and Read/Write EEPROM operations. For Block Register Write/Read operations, the I²C master can individually access addressed registers that are made of an 8-bit data byte. The offset of the indexed register is encoded in the register address, as described in Table 1.

8.5.2 Block Register Write

The I²C Block Register Write transaction is illustrated in Figure 30 and consists of the following sequence.

1. Master issues a Start Condition.
2. Master writes the 7-bit Slave Address following by a Write bit.
3. Master writes the 8-bit Register address as the CommandCode of the programming sequence.
4. Master writes one or more data bytes each of which should be acknowledged by the slave. The slave increments the internal register address after each byte.
5. Master issues a Stop Condition to terminate the transaction.

Figure 30. Block Register Write Programming Sequence

8.5.3 Block Register Read

The I²C Block Register Read transaction is illustrated in Figure 31 and consists of the following sequence.

1. Master issues a Start Condition.
2. Master writes the 7-bit Slave Address followed by a Write bit.
3. Master writes the 8-bit Register address as the CommandCode of the programming sequence.
4. Master issues a Repeated Start Condition.
5. Master writes the 7-bit Slave Address following by a Read bit.
6. Slave returns one or more data bytes as long as the Master continues to acknowledge them. The slave increments the internal register address after each byte.
7. Master issues a Stop Condition to terminate the transaction.

Figure 31. Block Register Read Programming Sequence

8.5.4 Write SRAM

The on-chip SRAM is a volatile, shadow memory array used to temporarily store register data, and is intended only for programming the non-Volatile EEPROM. The SRAM has the identical data format as the EEPROM map. The register configuration data can be transferred to the SRAM array through special memory access registers in the register map. To successfully program the SRAM, the complete base array and at least one page should be written. The following details the programming sequence to transfer the device registers into the SRAM.

1. Program the device registers to match a desired setting.
2. Write a 1 to R49.6. This ensures that the device registers are copied to the SRAM.

The SRAM can also be written with particular values according to the following programming sequence.

1. Write the SRAM address in R51.
2. Write the desired data byte in R53 in the same I²C transaction and this data byte will be written to the address specified in the step above. Any additional access that is part of the same transaction will cause the SRAM address to be incremented and a write will take place to the next SRAM address. Access to SRAM will terminate at the end of current I²C transaction.

8.5.5 Write EEPROM

The on-chip EEPROM is a non-Volatile memory array used to permanently store register data for a custom device start-up configuration setting to initialize registers upon power up or POR. The EEPROM is comprised of bits shown in the EEPROM Map. The transfer must first happen to the SRAM and then to the EEPROM. During EEPROM write, R49.2 is a 1 and the EEPROM contents cannot be accessed. The following details the programming sequence to transfer the entire contents of SRAM to EEPROM.

1. Make sure the Write SRAM procedure (Write SRAM) was done to commit the register settings to the SRAM with start-up configurations intended for programming to the EEPROM.
2. Write 0xBE to R56. This provides basic protection from inadvertent programming of EEPROM.
3. Write a 1 to R49.0. This programs the entire SRAM contents to EEPROM. Once completed, the contents in R48 will increment by 1. R48 contains the total number of EEPROM programming cycles that are successfully completed.
4. Write 0x00 to R56 to protect against inadvertent programming of EEPROM.

8.5.6 Read SRAM

The contents of the SRAM can be read out, one word at a time, starting with that of the requested address. Following details the programming sequence for an SRAM read by address.

1. Write the SRAM address in R51.
2. The SRAM data located at the address specified in the step above can be obtained by reading R53 in the same I²C transaction. Any additional access that is part of the same transaction will cause the SRAM address to be incremented and a read will take place of the next SRAM address. Access to SRAM will terminate at the end of current I²C transaction.

8.5.7 Read EEPROM

The contents of the EEPROM can be read out, one word at a time, starting with that of the requested address. Following details the programming sequence for an EEPROM read by address.

1. Write the EEPROM address in R51.
2. The EEPROM data located at the address specified in the step above can be obtained by reading R52 in the same I²C transaction. Any additional access that is part of the same transaction will cause the EEPROM address to be incremented and a read will take place of the next EEPROM address. Access to EEPROM will terminate at the end of current I²C transaction.

8.7.1 Register Descriptions

9.2.1 Jitter Considerations in Serdes Systems

Jitter-sensitive applications such as 10-Gbps or 100-Gbps Ethernet, deploy a serial link using a Serializer in the transmit section (TX) and a De-serializer in the receive section (RX). These SERDES blocks are typically embedded in an ASIC or FPGA. Estimating the clock jitter impact on the link budget requires understanding of the TX PLL bandwidth and the RX CDR bandwidth.

As can be seen in Figure 32, the pass band region between the TX low-pass cutoff and RX high-pass cutoff frequencies is the range over which the reference clock jitter adds without any attenuation to the jitter budget of the link. Outside of these frequencies, the SERDES link will attenuate the reference clock jitter with a 20 dB/dec or even steeper roll-off. Modern ASIC or FPGA designs have some flexibility on deciding the optimal RX CDR bandwidth and TX PLL bandwidth. These bandwidths are typically set based on what is achievable in the ASIC or FPGA process node, without increasing design complexity, and on any jitter tolerance or wander specification that needs to be met, as related to the RX CDR bandwidth.

The overall allowable jitter in a serial link is dictated by IEEE or other relevant standards. For example, IEEE802.3ba states that the maximum transmit jitter (peak-peak) for 10-Gbps Ethernet should be no more than 0.28 × UI and this equates to a 27.1516 ps, p-p for the overall allowable transmit jitter.

The jitter contributing elements are made up of the reference clock, generated potentially from a device like LMK61E2, the transmit medium, transmit driver, and so forth. Only a portion of the overall allowable transmit jitter is allocated to the reference clock, typically 20% or lower. Therefore, the allowable reference clock jitter, for a 20% clock jitter budget, is 5.43 ps, p-p.

Jitter in a reference clock is made up of deterministic jitter (arising from spurious signals due to supply noise or mixing from other outputs or from the reference input) and random jitter (usually due to thermal noise and other uncorrelated noise sources). A typical clock tree in a serial link system consists of clock generators and fanout buffers. The allowable reference clock jitter of 5.43 ps, p-p is needed at the output of the fanout buffer. Modern fanout buffers have low-additive random jitter (less than 100 fs RMS) with no substantial contribution to the deterministic jitter. Therefore, the clock generator and fanout buffer contribute to the random jitter while the primary contributor to the deterministic jitter is the clock generator. Rule of thumb, for modern clock generators, is to allocate 25% of allowable reference clock jitter to the deterministic jitter and 75% to the random jitter. This amounts to an allowable deterministic jitter of 1.36 ps, p-p and an allowable random jitter of 4.07 ps, p-p. For serial link systems that need to meet a bit error rate (BER) of 10^–12, the allowable random jitter in root-mean-square is 0.29 ps RMS. This is calculated by dividing the p-p jitter by 14 for a BER of 10^–12. Accounting for random jitter from the fanout buffer, the random jitter needed from the clock generator is 0.27 ps RMS. This is calculated by the root-mean-square subtraction from the desired jitter at the fanout buffer's output assuming 100 fs RMS of additive jitter from the fanout buffer.

With careful frequency planning techniques, like spur optimization (covered in Spur Mitigation Techniques ) and on-chip LDOs to suppress supply noise, the LMK61E2 is able to generate clock outputs with deterministic jitter that is below 1 ps, p-p and random jitter that is below 0.2 ps RMS. This gives the serial link system with additional margin on the allowable transmit jitter resulting in a BER better than 10^–12.

Figure 32. Dependence of Clock Jitter in Serial Links

9.2.2 Frequency Margining

9.2.2.2 Coarse Frequency Margining

Certain systems require the processors to be tested at clock frequencies that are slower or faster by 5% or 10%. The LMK61E2 offers the ability to change its output divider for the desired change from its nominal output frequency as explained in the High-Speed Output Divider section.

Figure 33. System Implementation With Clock Compensation for Standards Compliance

9.2.3 Design Requirements

Consider a typical wired communications application, like a top-of-rack switch, which needs to clock high data rate 10-Gbps or 100-Gbps Ethernet PHYs. In such systems, the clock is expected to be available upon power up without the need for any device-level programming. An example of such a clock frequency would be a 156.25 MHz in LVPECL output format.

The Detailed Design Procedure below describes the detailed design procedure to generate the required output frequencies for the above scenario using LMK61E2.