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  • LMK03328 具有两个独立 PLL、八路输出、集成 EEPROM 的超低抖动时钟发生器

    • ZHCSE36E August   2015  – September 2024 LMK03328

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  • LMK03328 具有两个独立 PLL、八路输出、集成 EEPROM 的超低抖动时钟发生器
  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics - Power Supply
    7. 6.7  Pullable Crystal Characteristics (SECREF_P, SECREF_N)
    8. 6.8  Non-Pullable Crystal Characteristics (SECREF_P, SECREF_N)
    9. 6.9  Clock Input Characteristics (PRIREF_P/PRIREF_N, SECREF_P/SECREF_N)
    10. 6.10 VCO Characteristics
    11. 6.11 PLL Characteristics
    12. 6.12 1.8-V LVCMOS Output Characteristics (OUT[7:0])
    13. 6.13 LVCMOS Output Characteristics (STATUS[1:0]
    14. 6.14 Open-Drain Output Characteristics (STATUS[1:0])
    15. 6.15 AC-LVPECL Output Characteristics
    16. 6.16 AC-LVDS Output Characteristics
    17. 6.17 AC-CML Output Characteristics
    18. 6.18 HCSL Output Characteristics
    19. 6.19 Power-On/Reset Characteristics
    20. 6.20 2-Level Logic Input Characteristics (HW_SW_CTRL, PDN, GPIO[5:0])
    21. 6.21 3-Level Logic Input Characteristics (REFSEL, GPIO[3:1])
    22. 6.22 Analog Input Characteristics (GPIO[5])
    23. 6.23 I2C-Compatible Interface Characteristics (SDA, SCL)
    24. 6.24 Typical 156.25-MHz, Closed-Loop Output Phase Noise Characteristics
    25. 6.25 Typical 161.1328125-MHz, Closed-Loop Output Phase Noise Characteristics
    26. 6.26 Closed-Loop Output Jitter Characteristics
    27. 6.27 PCIe Clock Output Jitter
    28. 6.28 Typical Power Supply Noise Rejection Characteristics
    29. 6.29 Typical Power Supply Noise Rejection Characteristics
    30. 6.30 Typical Closed-Loop Output Spur Characteristics
    31. 6.31 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Test Configurations
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Block-Level Description
      2. 8.3.2 Device Configuration Control
        1. 8.3.2.1 Hard Pin Mode (HW_SW_CTRL = 1)
          1. 8.3.2.1.1 PLL Blocks
          2. 8.3.2.1.2 Output Buffer Auto Mute
          3. 8.3.2.1.3 Input Block
          4. 8.3.2.1.4 Channel Mux
          5. 8.3.2.1.5 Output Divider
          6. 8.3.2.1.6 Output Driver Format
          7. 8.3.2.1.7 Status MUX, Divider and Slew Rate
        2. 8.3.2.2 Soft Pin Programming Mode (HW_SW_CTRL = 0)
          1. 8.3.2.2.1 Device Config Space
          2. 8.3.2.2.2 PLL Blocks
          3. 8.3.2.2.3 Output Buffer Auto Mute
          4. 8.3.2.2.4 Input Block
          5. 8.3.2.2.5 Channel Mux
          6. 8.3.2.2.6 Output Divider
          7. 8.3.2.2.7 Output Driver Format
          8. 8.3.2.2.8 Status MUX, Divider, and Slew Rate
        3. 8.3.2.3 Register File Reference Convention
    4. 8.4 Device Functional Modes
      1. 8.4.1  Smart Input MUX
      2. 8.4.2  Universal Input Buffer (PRI_REF, SEC_REF)
      3. 8.4.3  Crystal Input Interface (SEC_REF)
      4. 8.4.4  Reference Doubler
      5. 8.4.5  Reference (R) Divider
      6. 8.4.6  Input (M) Divider
      7. 8.4.7  Feedback (N) Divider
      8. 8.4.8  Phase Frequency Detector (PFD)
      9. 8.4.9  Charge Pump
      10. 8.4.10 Loop Filter
      11. 8.4.11 VCO Calibration
      12. 8.4.12 Fractional Circuitry
        1. 8.4.12.1 Programmable Dithering Levels
        2. 8.4.12.2 Programmable Delta Sigma Modulator Order
      13. 8.4.13 Post Divider
      14. 8.4.14 High-Speed Output MUX
      15. 8.4.15 High-Speed Output Divider
      16. 8.4.16 High-Speed Clock Outputs
      17. 8.4.17 Output Synchronization
      18. 8.4.18 Status Outputs
        1. 8.4.18.1 Loss of Reference
        2. 8.4.18.2 Loss of Lock (LOL)
    5. 8.5 Programming
      1. 8.5.1 I2C Serial Interface
      2. 8.5.2 Block Register Write
      3. 8.5.3 Block Register Read
      4. 8.5.4 Write SRAM
      5. 8.5.5 Write EEPROM
      6. 8.5.6 Read SRAM
      7. 8.5.7 Read EEPROM
      8. 8.5.8 Read ROM
      9. 8.5.9 Default Device Configurations in EEPROM and ROM
  10. 9 Register Maps
    1. 9.1 LMK03328 Registers
      1. 9.1.1   VNDRID_BY1 Register; R0
      2. 9.1.2   VNDRID_BY0 Register; R1
      3. 9.1.3   PRODID Register; R2
      4. 9.1.4   REVID Register; R3
      5. 9.1.5   PARTID Register; R4
      6. 9.1.6   PINMODE_SW Register; R8
      7. 9.1.7   PINMODE_HW Register; R9
      8. 9.1.8   TARGETADR Register; R10
      9. 9.1.9   EEREV Register; R11
      10. 9.1.10  DEV_CTL Register; R12
      11. 9.1.11  INT_LIVE Register; R13
      12. 9.1.12  INT_MASK Register; R14
      13. 9.1.13  INT_FLAG_POL Register; R15
      14. 9.1.14  INT_FLAG Register; R16
      15. 9.1.15  INTCTL Register; R17
      16. 9.1.16  OSCCTL2 Register; R18
      17. 9.1.17  STATCTL Register; R19
      18. 9.1.18  MUTELVL1 Register; R20
      19. 9.1.19  MUTELVL2 Register; R21
      20. 9.1.20  OUT_MUTE Register; R22
      21. 9.1.21  STATUS_MUTE Register; R23
      22. 9.1.22  DYN_DLY Register; R24
      23. 9.1.23  REFDETCTL Register; R25
      24. 9.1.24  STAT0_INT Register; R27
      25. 9.1.25  STAT1 Register; R28
      26. 9.1.26  OSCCTL1 Register; R29
      27. 9.1.27  PWDN Register; R30
      28. 9.1.28  OUTCTL_0 Register; R31
      29. 9.1.29  OUTCTL_1 Register; R32
      30. 9.1.30  OUTDIV_0_1 Register; R33
      31. 9.1.31  OUTCTL_2 Register; R34
      32. 9.1.32  OUTCTL_3 Register; R35
      33. 9.1.33  OUTDIV_2_3 Register; R36
      34. 9.1.34  OUTCTL_4 Register; R37
      35. 9.1.35  OUTDIV_4 Register; R38
      36. 9.1.36  OUTCTL_5 Register; R39
      37. 9.1.37  OUTDIV_5 Register; R40
      38. 9.1.38  OUTCTL_6 Register; R41
      39. 9.1.39  OUTDIV_6 Register; R42
      40. 9.1.40  OUTCTL_7 Register; R43
      41. 9.1.41  OUTDIV_7 Register; R44
      42. 9.1.42  CMOSDIVCTRL Register; R45
      43. 9.1.43  CMOSDIV0 Register; R46
      44. 9.1.44  CMOSDIV1 Register; R47
      45. 9.1.45  STATUS_SLEW Register; R49
      46. 9.1.46  IPCLKSEL Register; R50
      47. 9.1.47  IPCLKCTL Register; R51
      48. 9.1.48  PLL1_RDIV Register; R52
      49. 9.1.49  PLL1_MDIV Register; R53
      50. 9.1.50  PLL2_RDIV Register; R54
      51. 9.1.51  PLL2_MDIV Register; R55
      52. 9.1.52  PLL1_CTRL0 Register; R56
      53. 9.1.53  PLL1_CTRL1 Register; R57
      54. 9.1.54  PLL1_NDIV_BY1 Register; R58
      55. 9.1.55  PLL1_NDIV_BY0 Register; R59
      56. 9.1.56  PLL1_FRACNUM_BY2 Register; R60
      57. 9.1.57  PLL1_FRACNUM_BY1 Register; R61
      58. 9.1.58  PLL1_FRACNUM_BY0 Register; R62
      59. 9.1.59  PLL_FRACDEN_BY2 Register; R63
      60. 9.1.60  PLL1_FRACDEN_BY1 Register; R64
      61. 9.1.61  PLL1_FRACDEN_BY0 Register; R65
      62. 9.1.62  PLL1_MASHCTRL Register; R66
      63. 9.1.63  PLL1_LF_R2 Register; R67
      64. 9.1.64  PLL1_LF_C1 Register; R68
      65. 9.1.65  PLL1_LF_R3 Register; R69
      66. 9.1.66  PLL1_LF_C3 Register; R70
      67. 9.1.67  PLL2_CTRL0 Register; R71
      68. 9.1.68  PLL2_CTRL1 Register; R72
      69. 9.1.69  PLL2_NDIV_BY1 Register; R73
      70. 9.1.70  PLL2_NDIV_BY0 Register; R74
      71. 9.1.71  PLL2_FRACNUM_BY2 Register; R75
      72. 9.1.72  PLL2_FRACNUM_BY1 Register; R76
      73. 9.1.73  PLL2_FRACNUM_BY0 Register; R77
      74. 9.1.74  PLL2_FRACDEN_BY2 Register; R78
      75. 9.1.75  PLL2_FRACDEN_BY1 Register; R79
      76. 9.1.76  PLL2_FRACDEN_BY0 Register; R80
      77. 9.1.77  PLL2_MASHCTRL Register; R81
      78. 9.1.78  PLL2_LF_R2 Register; R82
      79. 9.1.79  PLL2_LF_C1 Register; R83
      80. 9.1.80  PLL2_LF_R3 Register; R84
      81. 9.1.81  PLL2_LF_C3 Register; R85
      82. 9.1.82  XO_MARGINING Register; R86
      83. 9.1.83  XO_OFFSET_GPIO5_STEP_1_BY1 Register; R88
      84. 9.1.84  XO_OFFSET_GPIO5_STEP_1_BY0 Register; R89
      85. 9.1.85  XO_OFFSET_GPIO5_STEP_2_BY1 Register; R90
      86. 9.1.86  XO_OFFSET_GPIO5_STEP_2_BY0 Register; R91
      87. 9.1.87  XO_OFFSET_GPIO5_STEP_3_BY1 Register; R92
      88. 9.1.88  XO_OFFSET_GPIO5_STEP_3_BY0 Register; R93
      89. 9.1.89  XO_OFFSET_GPIO5_STEP_4_BY1 Register; R94
      90. 9.1.90  XO_OFFSET_GPIO5_STEP_4_BY0 Register; R95
      91. 9.1.91  XO_OFFSET_GPIO5_STEP_5_BY1 Register; R96
      92. 9.1.92  XO_OFFSET_GPIO5_STEP_5_BY0 Register; R97
      93. 9.1.93  XO_OFFSET_GPIO5_STEP_6_BY1 Register; R98
      94. 9.1.94  XO_OFFSET_GPIO5_STEP_6_BY0 Register; R99
      95. 9.1.95  XO_OFFSET_GPIO5_STEP_7_BY1 Register; R100
      96. 9.1.96  XO_OFFSET_GPIO5_STEP_7_BY0 Register; R101
      97. 9.1.97  XO_OFFSET_GPIO5_STEP_8_BY1 Register; R102
      98. 9.1.98  XO_OFFSET_GPIO5_STEP_8_BY0 Register; R103
      99. 9.1.99  XO_OFFSET_SW_BY1 Register; R104
      100. 9.1.100 XO_OFFSET_SW_BY0 Register; R105
      101. 9.1.101 PLL1_CTRL2 Register; R117
      102. 9.1.102 PLL1_CTRL3 Register; R118
      103. 9.1.103 PLL1_CALCTRL0 Register; R119
      104. 9.1.104 PLL1_CALCTRL1 Register; R120
      105. 9.1.105 PLL2_CTRL2 Register; R131
      106. 9.1.106 PLL2_CTRL3 Register; R132
      107. 9.1.107 PLL2_CALCTRL0 Register; R133
      108. 9.1.108 PLL2_CALCTRL1 Register; R134
      109. 9.1.109 NVMSCRC Register; R135
      110. 9.1.110 NVMCNT Register; R136
      111. 9.1.111 NVMCTL Register; R137
      112. 9.1.112 NVMLCRC Register; R138
      113. 9.1.113 MEMADR_BY1 Register; R139
      114. 9.1.114 MEMADR_BY0 Register; R140
      115. 9.1.115 NVMDAT Register; R141
      116. 9.1.116 RAMDAT Register; R142
      117. 9.1.117 ROMDAT Register; R143
      118. 9.1.118 NVMUNLK Register; R144
      119. 9.1.119 REGCOMMIT_PAGE Register; R145
      120. 9.1.120 POR_CTRL Register; R173
      121. 9.1.121 XOCAPCTRL_BY1 Register; R199
      122. 9.1.122 XOCAPCTRL_BY0 Register; R200
    2. 9.2 EEPROM Map
  11. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Jitter Considerations in SERDES Systems
      2. 10.1.2 Frequency Margining
        1. 10.1.2.1 Fine Frequency Margining
        2. 10.1.2.2 Coarse Frequency Margining
    2. 10.2 Typical Applications
      1. 10.2.1 Application Block Diagram Examples
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Device Selection
            1. 10.2.1.2.1.1 Calculation Using LCM
          2. 10.2.1.2.2 Device Configuration
          3. 10.2.1.2.3 PLL Loop Filter Design
            1. 10.2.1.2.3.1 PLL Loop Filter Design
          4. 10.2.1.2.4 PLL and Clock Output Assignment
          5. 10.2.1.2.5 Spur Mitigation Techniques
            1. 10.2.1.2.5.1 Phase Detector Spurs
            2. 10.2.1.2.5.2 Integer Boundary Fractional Spurs
            3. 10.2.1.2.5.3 Primary Fractional Spurs
            4. 10.2.1.2.5.4 Sub-Fractional Spurs
    3. 10.3 Power Supply Recommendations
      1. 10.3.1 Device Power-Up Sequence
      2. 10.3.2 Device Power-Up Timing
      3. 10.3.3 Power Down
      4. 10.3.4 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
        1. 10.3.4.1 Mixing Supplies
        2. 10.3.4.2 Power-On Reset
        3. 10.3.4.3 Powering Up From Single-Supply Rail
        4. 10.3.4.4 Powering Up From Split-Supply Rails
        5. 10.3.4.5 Slow Power-Up Supply Ramp
        6. 10.3.4.6 Non-Monotonic Power-Up Supply Ramp
        7. 10.3.4.7 Slow Reference Input Clock Start-Up
      5. 10.3.5 Power Supply Bypassing
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
        1. 10.4.1.1 Assess Thermal Reliability
        2. 10.4.1.2 Support for PCB Temperature up to 105°C
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
  15. 重要声明
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LMK03328 具有两个独立 PLL、八路输出、集成 EEPROM 的超低抖动时钟发生器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

下载最新的英语版本

1 特性

  • 超低噪声、高性能
    • 抖动：fOUT > 100MHz 时的典型值为 100fs RMS
    • PSNR：–80dBc，具有强大的抗电源噪声能力
  • 灵活的器件选项
    • 多达 8 路 AC-LVPECL、AC-LVDS、AC-CML、HCSL 或 LVCMOS 输出或任意组合
    • 引脚模式、I2C 模式、EEPROM 模式
    • 71 引脚可选择预编程默认启动选项
  • 双路输入，自动或手动选择
    • 晶振输入：10MHz 至 52MHz
    • 外部输入：1MHz 至 300MHz
  • 频率裕量选项
    • 精调频率裕度（典型值为 ±50ppm），采用低成本可牵引晶振基准
    • 无毛刺脉冲的粗调频率裕度 (%)，采用输出分频器
  • 其他特性
    • 电源：3.3V 内核、1.8V、2.5V 或 3.3V 输出
    • 工业级温度范围（-40°C 至 85°C）
    • 封装：7mm × 7mm 48-WQFN

2 应用

  • 交换机和路由器
  • 网络与电信线卡
  • 服务器和存储系统
  • 无线基站
  • PCIe 第 1 代、第 2 代、第 3 代、第 4 代、第 5 代、第 6 代
  • 测试和测量
  • 广播基础设施

3 说明

LMK03328 器件是一款超低噪声时钟发生器，具有两个带集成式 VCO、灵活时钟分配和扇出的分数 N 频率合成器，在片上 EEPROM 中存储有引脚可选配置状态。该器件可为各种千兆位级串行接口和数字器件提供多个时钟，从而通过替代多个振荡器和时钟分配器件来降低 BOM 成本、减小电路板面积以及提高可靠性。超低抖动可降低高速串行链路中的比特误码率 (BER)。

封装信息
器件型号 封装(1) 封装尺寸(2)
LMK03328 RHS（WQFN，48） 7.00mm × 7.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。
(2) 封装尺寸（长 × 宽）为标称值，并包括引脚（如适用）。
LMK03328 LMK03328 简化版方框图 LMK03328 简化版方框图

4 Device Comparison

Table 4-1 LVPECL Output Jitter Over Different Integration Bandwidths
OUTPUT FREQUENCY (MHz)INTEGRATION BANDWIDTHTYPICAL JITTER (ps, rms)
< 10012 kHz - 5 MHz0.15
> 1001 kHz – 5 MHz
12 kHz – 20 MHz		0.1

5 Pin Configuration and Functions

LMK03328 RHS Package48-Pin WQFNTop View Figure 5-1 RHS Package48-Pin WQFNTop View
Table 5-1 Pin Functions
NO. NAME TYPE DESCRIPTION
POWER
— DAP Ground Die Attach Pad.
The DAP is an electrical connection and provides a thermal dissipation path. For proper electrical and thermal performance of the device, a 6x6 via pattern (0.3-mm holes) is recommended to connect the DAP to PCB ground layers. Refer to Layout Guidelines.
4 VDD_DIG Analog 3.3-V Power Supply for Digital Control and STATUS outputs.
5 VDD_IN Analog 3.3-V Power Supply for Input Block.
18 VDDO_01 Analog 1.8-V, 2.5-V, 3.3-V Power Supply for OUT0/OUT1 channel.
19 VDDO_23 Analog 1.8-V, 2.5-V, 3.3-V Power Supply for OUT2/OUT3 channel.
27 VDD_PLL2 Analog 3.3-V Power Supply for PLL2.
36 VDD_PLL1 Analog 3.3-V Power Supply for PLL1.
37 VDDO_4 Analog 1.8-V, 2.5-V, 3.3-V Power Supply for OUT4 channel.
40 VDDO_5 Analog 1.8-V, 2.5-V, 3.3-V Power Supply for OUT5 channel.
43 VDDO_6 Analog 1.8-V, 2.5-V, 3.3-V Power Supply for OUT6 channel.
46 VDDO_7 Analog 1.8-V, 2.5-V, 3.3-V Power Supply for OUT7 channel.
INPUT BLOCK
6 PRIREF_P Universal Primary reference clock.
Accepts a differential or single-ended input. Input pins have internal AC-coupling capacitors and biasing. For LVCMOS input, the non-driven input pin must be pulled down to ground.
7 PRIREF_N
8 REFSEL LVCMOS Manual reference input selection for PLL1 and PLL2 (3-state).
Weak pullup resistor.
9 HW_SW_CTRL LVCMOS Selection for Hard Pin Mode (ROM), Soft Pin Mode (EEPROM), or Register Default Mode.
Weak pullup resistor.
10 SECREF_P Universal Secondary reference clock.
Accepts a differential or single-ended input or Crystal input. Input pins have internal AC-coupling capacitors and biasing. For LVCMOS input, external input termination is required to attenuate the swing to less than 2.6 V, and the non-driven input pin must be pulled down to ground.
For crystal input, the AT cut fundamental crystal must be used as per defined spec and the pullable crystal must be used for fine margining.
11 SECREF_N
SYNTHESIZER BLOCK
3 CAP_DIG Analog External Bypass Capacitor for digital blocks. Attach a 10 µF to GND.
28 CAP_PLL2 Analog External Bypass Capacitor for PLL2. Attach a 10 µF to GND.
29 LF2 Analog External Loop Filter for PLL2.
34 LF1 Analog External Loop Filter for PLL1.
35 CAP_PLL1 Analog External Bypass Capacitor for PLL1. Attach a 10 µF to GND.
OUTPUT BLOCK
14 OUT0_P Universal Differential/LVCMOS Output Pair 0. Programmable driver with differential or 2x 1.8-V LVCMOS outputs.
15 OUT0_N
17 OUT1_P Universal Differential/LVCMOS Output Pair 1. Programmable driver with differential or 2x 1.8-V LVCMOS outputs.
16 OUT1_N
20 OUT2_P Universal Differential/LVCMOS Output Pair 2. Programmable driver with differential or 2x 1.8-V LVCMOS outputs.
21 OUT2_N
23 OUT3_P Universal Differential/LVCMOS Output Pair 3. Programmable driver with differential or 2x 1.8-V LVCMOS outputs.
22 OUT3_N
39 OUT4_P Universal Differential/LVCMOS Output Pair 4. Programmable driver with differential or 2x 1.8-V LVCMOS outputs.
38 OUT4_N
42 OUT5_P Universal Differential/LVCMOS Output Pair 5. Programmable driver with differential or 2x 1.8-V LVCMOS outputs.
41 OUT5_N
45 OUT6_P Universal Differential/LVCMOS Output Pair 6. Programmable driver with differential or 2x 1.8-V LVCMOS outputs.
44 OUT6_N
48 OUT7_P Universal Differential/LVCMOS Output Pair 7. Programmable driver with differential or 2x 1.8-V LVCMOS outputs.
47 OUT7_N
DIGITAL CONTROL / INTERFACES(1)
1 STATUS0 Universal Status Output 0 (open-drain, requires external pullup) or 3.3-V LVCMOS output from synth (push-pull). Status signal selection and output polarity are programmable.
2 STATUS1 Universal Status Output 1 (open-drain, requires external pullup) or 3.3-V LVCMOS output from synth (push-pull). Status signal selection and output polarity are programmable.
12 GPIO0 LVCMOS Multifunction Inputs (2-state).
13 PDN LVCMOS Device Power-down (active low). Weak pullup resistor.
33 GPIO5 Universal Multifunction Input (2-state) or Analog input for frequency margin.
24 GPIO1 LVCMOS Multifunction Input (3-state or 2-state).
25 SDA LVCMOS I2C Serial Data (bidirectional, open-drain). Requires an external pullup resistor to VDD_DIG. I2C target address is initialized from on-chip EEPROM.
26 SCL LVCMOS I2C Serial Clock (bidirectional, open-drain). Requires an external pullup resistor to VDD_DIG.
30 GPIO2 LVCMOS Multifunction Input (3-state or 2-state).
31 GPIO3 LVCMOS Multifunction Input (3-state or 2-state).
32 GPIO4 LVCMOS Multifunction Input (2-state).
(1) Refer to Device Configuration Control for details on the digital control and interfaces.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MINMAXUNIT
Supply voltage for Input, Synthesizer, Control, and Output Blocks, VDD_IN, VDD_PLL1, VDD_PLL2, VDD_DIG, VDDO_x–0.33.6V
Input voltage for clock and logic inputs, VIN–0.3VDD + 0.3V
Output voltage for clock and logic outputs, VOUT–0.3VDD + 0.3V
Junction temperature, TJ150°C
Storage temperature, Tstg–65150°C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

6.2 ESD Ratings

VALUEUNIT
V(ESD)Electrostatic dischargeHuman-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)±2000V
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)±500
(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD_IN, VDD_PLL1, VDD_PLL2, VDD_DIG Supply Voltage for Input, Analog, Control Blocks 3.135 3.3 3.465 V
VDDO_x Supply Voltage for Output Drivers (Differential, LVCMOS).(1) 1.7 1.8 3.465 V
1.7 2.5 3.465
1.7 3.3 3.465
TA Ambient Temperature –40 25 85 °C
TJ Junction Temperature 125 °C
dVDD/dt Maximum VDD Power-Up Ramp 0.1 100 ms
WR EEPROM number of writes 100
(1) The 3 different NOM values are the 3 typical test voltages throughout the data sheet.

6.4 Thermal Information

THERMAL METRIC(1) LMK03328(2) (3) (4) UNIT
RHS (WQFN)
48 PINS
Airflow (LFM) 0 Airflow (LFM) 200 Airflow (LFM) 400
RθJA Junction-to-ambient thermal resistance 26.47 16.4 14.62 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 16.57 n/a n/a °C/W
RθJB Junction-to-board thermal resistance 6.84 n/a n/a °C/W
ψJT Junction-to-top characterization parameter 0.23 0.31 0.47 °C/W
ψJB Junction-to-board characterization parameter 4.02 3.86 3.84 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.06 n/a n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note.
(2) The package thermal resistance is calculated on a 4-layer JEDEC board.
(3) Package DAP connected to PCB GND plane with 16 thermal vias (0.3-mm diameter).
(4) ψJB (junction to board) is used when the main heat flow is from the junction to the GND pad. See Layout for more information on providing good system reliability and quality.

6.5 Thermal Information

THERMAL METRIC(1)CONDITIONLMK03328UNIT
RHS (WQFN)
48 PINS
RθJAJunction-to-ambient thermal resistance10-layer 200 mm × 250 mm board, 36 thermal vias, Airflow = 0 LFM10°C/W
ψJBJunction-to-board characterization parameter10-layer 200 mm × 250 mm board, 36 thermal vias, Airflow = 0 LFM2.8°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).

 
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