• Menu
  • Product
  • Email
  • PDF
  • Order now

  • DRV2605 用于具有内置库和智能环路架构的 ERM 和 LRA 触觉驱动器

    • ZHCSCW9E December   2012  – April 2018 DRV2605

      PRODUCTION DATA.  

  • CONTENTS
  • SEARCH
  • DRV2605 用于具有内置库和智能环路架构的 ERM 和 LRA 触觉驱动器
  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Support for ERM and LRA Actuators
      2. 7.3.2  Smart-Loop Architecture
        1. 7.3.2.1 Auto-Resonance Engine for LRA
        2. 7.3.2.2 Real-Time Resonance-Frequency Reporting for LRA
        3. 7.3.2.3 Automatic Overdrive and Braking
          1. 7.3.2.3.1 Startup Boost
          2. 7.3.2.3.2 Brake Factor
          3. 7.3.2.3.3 Brake Stabilizer
        4. 7.3.2.4 Automatic Level Calibration
          1. 7.3.2.4.1 Automatic Compensation for Resistive Losses
          2. 7.3.2.4.2 Automatic Back-EMF Normalization
          3. 7.3.2.4.3 Calibration Time Adjustment
          4. 7.3.2.4.4 Loop-Gain Control
          5. 7.3.2.4.5 Back-EMF Gain Control
        5. 7.3.2.5 Actuator Diagnostics
      3. 7.3.3  Open-Loop Operation for LRA
      4. 7.3.4  Open-Loop Operation for ERM
      5. 7.3.5  Flexible Front-End Interface
        1. 7.3.5.1 PWM Interface
        2. 7.3.5.2 Internal Memory Interface
          1. 7.3.5.2.1 Waveform Sequencer
          2. 7.3.5.2.2 Library Parameterization
        3. 7.3.5.3 Real-Time Playback (RTP) Interface
        4. 7.3.5.4 Analog Input Interface
        5. 7.3.5.5 Audio-to-Vibe Interface
        6. 7.3.5.6 Input Trigger Option
          1. 7.3.5.6.1 I2C Trigger
          2. 7.3.5.6.2 Edge Trigger
          3. 7.3.5.6.3 Level Trigger
      6. 7.3.6  Edge Rate Control
      7. 7.3.7  Constant Vibration Strength
      8. 7.3.8  Battery Voltage Reporting
      9. 7.3.9  One-Time Programmable (OTP) Memory for Configuration
      10. 7.3.10 Low-Power Standby
      11. 7.3.11 Device Protection
        1. 7.3.11.1 Thermal Protection
        2. 7.3.11.2 Overcurrent Protection of the Actuator
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power States
        1. 7.4.1.1 Operation With VDD < 2.5 V (Minimum VDD)
        2. 7.4.1.2 Operation With VDD > 6 V (Absolute Maximum VDD)
        3. 7.4.1.3 Operation With EN Control
        4. 7.4.1.4 Operation With STANDBY Control
        5. 7.4.1.5 Operation With DEV_RESET Control
        6. 7.4.1.6 Operation in the Active State
      2. 7.4.2 Changing Modes of Operation
      3. 7.4.3 Operation of the GO Bit
      4. 7.4.4 Operation During Exceptional Conditions
        1. 7.4.4.1 Operation With No Actuator Attached
        2. 7.4.4.2 Operation With a Short at REG Pin
        3. 7.4.4.3 Operation With a Short at OUT+, OUT–, or Both
    5. 7.5 Programming
      1. 7.5.1 Auto-Resonance Engine Programming for the LRA
        1. 7.5.1.1 Drive-Time Programming
        2. 7.5.1.2 Current-Dissipation Time Programming
        3. 7.5.1.3 Blanking Time Programming
      2. 7.5.2 Automatic-Level Calibration Programming
        1. 7.5.2.1 Rated Voltage Programming
        2. 7.5.2.2 Overdrive Voltage-Clamp Programming
      3. 7.5.3 I2C Interface
        1. 7.5.3.1 TI Haptic Broadcast Mode
        2. 7.5.3.2 General I2C Operation
        3. 7.5.3.3 Single-Byte and Multiple-Byte Transfers
        4. 7.5.3.4 Single-Byte Write
        5. 7.5.3.5 Multiple-Byte Write and Incremental Multiple-Byte Write
        6. 7.5.3.6 Single-Byte Read
        7. 7.5.3.7 Multiple-Byte Read
      4. 7.5.4 Programming for Open-Loop Operation
        1. 7.5.4.1 Programming for ERM Open-Loop Operation
        2. 7.5.4.2 Programming for LRA Open-Loop Operation
      5. 7.5.5 Programming for Closed-Loop Operation
      6. 7.5.6 Auto Calibration Procedure
      7. 7.5.7 Programming On-Chip OTP Memory
      8. 7.5.8 Waveform Playback Programming
        1. 7.5.8.1 Data Formats for Waveform Playback
          1. 7.5.8.1.1 Open-Loop Mode
          2. 7.5.8.1.2 Closed-Loop Mode, Unidirectional
          3. 7.5.8.1.3 Closed-Loop Mode, Bidirectional
        2. 7.5.8.2 Waveform Setup and Playback
          1. 7.5.8.2.1 Waveform Playback Using RTP Mode
          2. 7.5.8.2.2 Waveform Playback Using the Analog-Input Mode
          3. 7.5.8.2.3 Waveform Playback Using PWM Mode
          4. 7.5.8.2.4 Waveform Playback Using Audio-to-Vibe Mode
          5. 7.5.8.2.5 Waveform Sequencer
          6. 7.5.8.2.6 Waveform Triggers
    6. 7.6 Register Map
      1. 7.6.1  Status (Address: 0x00)
        1. Table 4. Status Register Field Descriptions
      2. 7.6.2  Mode (Address: 0x01)
        1. Table 5. Mode Register Field Descriptions
      3. 7.6.3  Real-Time Playback Input (Address: 0x02)
        1. Table 6. Real-Time Playback Input Register Field Descriptions
      4. 7.6.4  (Address: 0x03)
        1. Table 7. Register Field Descriptions
      5. 7.6.5  Waveform Sequencer (Address: 0x04 to 0x0B)
        1. Table 8. Waveform Sequencer Register Field Descriptions
      6. 7.6.6  GO (Address: 0x0C)
        1. Table 9. GO Register Field Descriptions
      7. 7.6.7  Overdrive Time Offset (Address: 0x0D)
        1. Table 10. Overdrive Time Offset Register Field Descriptions
      8. 7.6.8  Sustain Time Offset, Positive (Address: 0x0E)
        1. Table 11. Sustain Time Offset, Positive Register Field Descriptions
      9. 7.6.9  Sustain Time Offset, Negative (Address: 0x0F)
        1. Table 12. Sustain Time Offset, Negative Register Field Descriptions
      10. 7.6.10 Brake Time Offset (Address: 0x10)
        1. Table 13. Brake Time Offset Register Field Descriptions
      11. 7.6.11 Audio-to-Vibe Control (Address: 0x11)
        1. Table 14. Audio-to-Vibe Control Register Field Descriptions
      12. 7.6.12 Audio-to-Vibe Minimum Input Level (Address: 0x12)
        1. Table 15. Audio-to-Vibe Minimum Input Level Register Field Descriptions
      13. 7.6.13 Audio-to-Vibe Maximum Input Level (Address: 0x13)
        1. Table 16. Audio-to-Vibe Maximum Input Level Register Field Descriptions
      14. 7.6.14 Audio-to-Vibe Minimum Output Drive (Address: 0x14)
        1. Table 17. Audio-to-Vibe Minimum Output Drive Register Field Descriptions
      15. 7.6.15 Audio-to-Vibe Maximum Output Drive (Address: 0x15)
        1. Table 18. Audio-to-Vibe Maximum Output Drive Register Field Descriptions
      16. 7.6.16 Rated Voltage (Address: 0x16)
        1. Table 19. Rated Voltage Register Field Descriptions
      17. 7.6.17 Overdrive Clamp Voltage (Address: 0x17)
        1. Table 20. Overdrive Clamp Voltage Register Field Descriptions
      18. 7.6.18 Auto-Calibration Compensation Result (Address: 0x18)
        1. Table 21. Auto-Calibration Compensation-Result Register Field Descriptions
      19. 7.6.19 Auto-Calibration Back-EMF Result (Address: 0x19)
        1. Table 22. Auto-Calibration Back-EMF Result Register Field Descriptions
      20. 7.6.20 Feedback Control (Address: 0x1A)
        1. Table 23. Feedback Control Register Field Descriptions
      21. 7.6.21 Control1 (Address: 0x1B)
        1. Table 24. Control1 Register Field Descriptions
      22. 7.6.22 Control2 (Address: 0x1C)
        1. Table 25. Control2 Register Field Descriptions
      23. 7.6.23 Control3 (Address: 0x1D)
        1. Table 26. Control3 Register Field Descriptions
      24. 7.6.24 Control4 (Address: 0x1E)
        1. Table 27. Control4 Register Field Descriptions
      25. 7.6.25 V(BAT) Voltage Monitor (Address: 0x21)
        1. Table 28. V(BAT) Voltage-Monitor Register Field Descriptions
      26. 7.6.26 LRA Resonance Period (Address: 0x22)
        1. Table 29. LRA Resonance-Period Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Actuator Selection
          1. 8.2.2.1.1 Eccentric Rotating-Mass Motors (ERM)
          2. 8.2.2.1.2 Linear Resonance Actuators (LRA)
            1. 8.2.2.1.2.1 Auto-Resonance Engine for LRA
        2. 8.2.2.2 Capacitor Selection
        3. 8.2.2.3 Interface Selection
        4. 8.2.2.4 Power Supply Selection
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Setup
      1. 8.3.1 Initialization Procedure
      2. 8.3.2 Typical Usage Examples
        1. 8.3.2.1 Play a Waveform or Waveform Sequence from the ROM Waveform Memory
        2. 8.3.2.2 Play a Real-Time Playback (RTP) Waveform
        3. 8.3.2.3 Play a PWM or Analog Input Waveform
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Trace Width
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 法律声明
    2. 11.2 波形库效果列表
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息
  13. 重要声明
search No matches found.
  • Full reading width
    • Full reading width
    • Comfortable reading width
    • Expanded reading width
  • Card for each section
  • Card with all content

 

DATA SHEET

DRV2605 用于具有内置库和智能环路架构的 ERM 和 LRA 触觉驱动器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 灵活触控反馈/Vibra 驱动程序
    • LRA（线性谐振致动器）
    • ERM（偏轴转动惯量)
  • 由 I2C 控制的数字回放引擎
    • 通过 I2C 实现的实时回放模式
  • 智能环路架构(1)
    • 自动过驱/制动 (ERM/LRA)
    • 自动谐振跟踪 (LRA)
    • 自动致动器诊断 (ERM/LRA)
    • 自动水平校准 (ERM/LRA)
  • 已获许可的 Immersion™TouchSense®2200 特性：
    • 集成 Immersion 效果库
    • 音频至气氛
  • 占空比控制范围介于 0% 至 100% 之间的可选脉宽调制 (PWM) 输入
  • 可选模拟输入控制
  • 可选硬件触发引脚
  • 高效输出驱动
  • 快速启动时间
  • 电源电压上的持续加速
  • 1.8V 兼容，VDD 容限数字引脚 (1)
    • 1. 正在申请专利的控制算法

2 应用

  • 手机和平板电脑
  • 手表和可穿戴技术
  • 远程控制、鼠标和外设器件
  • 支持触觉反馈的器件
  • 人机界面

3 说明

DRV2605 器件设计用于通过共享的 I2C 兼容总线提供极为灵活的 ERM 和 LRA 传动器触控。该控制使得主机处理器不用再生成脉宽调制 (PWM) 驱动信号，从而节省了代价高昂的定时器中断和硬件引脚。

DRV2605 器件具有内容丰富的集成库，可提供来自 ERM 和 LRA Immersion 的 100 多种已获许可的效果，从而免除了对设计触控波形的需要。

DRV2605 器件可提供许可版本的 Immersion TouchSense 2200 软件，其中包括 2200 效果库和 2200 音频至气氛 功能。此外，主机处理器可利用实时回放模式绕过库回放引擎并通过 I2C 从主机直接播放波形。

DRV2605 器件还包含一个智能环路架构，此架构可轻松实现 LRA 自动谐振驱动以及优化反馈的 ERM 驱动。这种反馈提供了自动过驱和制动，从而生成了一个简化的输入波形图并实现了可靠的电机控制和稳定的电机性能。音频至触觉模式自动将音频输入信号转换为实际的触控效果。

DRV2605 器件 具有 一个经三重调制的输出级，从而能够提供比基于线性的输出驱动器更高的效率。DRV2605 器件采用 9 焊球 WCSP 封装，具有很少的组件数量，操作灵活，是支持触控的便携式振动和触觉 应用的理想选择。

有关 Immersion 软件的重要说明，请参阅 法律声明 部分。

器件信息(1)

器件型号 封装 封装尺寸（最大值）
DRV2605 DSBGA (9) 1.50mm x 1.50mm
  1. 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。
DRV2605 simplifiedSchematic_slos854.gif

4 修订历史记录

Changes from D Revision (December 2015) to E Revision

  • Changed the DEFAULT value for bit 5-4 of Table 25 From: 1 To 3 Go
  • Changed the DEFAULT value for bit 3-2 of Table 25 From: 2 To 1 Go
  • Changed the DEFAULT value for bit 1-0 of Table 25 From: 2 To 1 Go
  • Changed the typical value of C(VDD) in Table 30 From: 0.1 µF To: 1 µFGo
  • Changed C(VDD) from 0.1 to 1 µF in Figure 56Go
  • Changed the input-voltage supply range From: 2 V to 5.2 V To: 2.5 V to 5.5 V in the Power Supply Recommendations sectonGo

Changes from C Revision (September 2014) to D Revision

  • Changed th(1) Hold time, SCL to SDA from 10 ns to 50 ns in Timing RequirementsGo
  • Changed the default value of NG_THRESH[1:0] from 1 to 2 in the Register MapControl3 Register Field DescriptionsGo

Changes from B Revision (February 2014) to C Revision

  • Changed 将特性 项目符号从免专利费集成 Immersion 库更改为波形事件序列生成器和触发器Go
  • Changed 特性项目符号从音频至触觉模式更改为顶级：经许可的 Immersion TouchSense 2200 特性：Go
  • Changed 从音频至触觉模式更改为音频至气氛Go
  • Changed 更改了 说明 的第二段，用于澄清。Go
  • Updated document to new datasheet styleGo
  • Deleted Operating free-air temperature range, TA (information replaced by Thermal Information table) Go
  • Changed EN pulldown resistance added to Electrical CharacteristicsGo
  • Changed connection terminal of input impedance from GND to V(CM_ANA) in Electrical Characteristics sectionGo
  • Moved switching parameters to new Switching Characteristics table Go
  • Added TI Haptic Broadcast Mode sectionGo
  • Changed AC couple capacitor recommendation from 0.1 µF to 1 µF to be consistent with Recommended External Components table.Go
  • Added Immersion 法律声明 Go

Changes from A Revision (March 2013) to B Revision

  • Changed 从一页数据表更改为产品文件夹中的全部数据表Go

Changes from * Revision (December 2012) to A Revision

  • Changed minimum supported resonant frequency from 50 Hz to 125 Hz Go
  • Added digital pulldown resistance parameter to Electrical CharacteristicsGo
  • Changed |IIH| MAX value from 3 to 3.5µA per CMS #C1303020Go
  • Changed calibration diagram to include DRIVE_TIME into ERM requirementsGo
  • Changed bitfield name from "LRA_DRIVE_MODE" to "OTP_STATUS"Go
  • Changed C(REG) from 0.1 to 1 µF in Figure 56Go

5 Pin Configuration and Functions

YZF Package
9-Pin DSBGA With 0.5-mm Pitch
(Top View)

Pin Functions

PIN TYPE(1) DESCRIPTION
NO. NAME
A1 EN I Device enable
A2 REG O The REG pin is the 1.8-V regulator output. A 1-µF capacitor is required.
A3 OUT+ O Positive haptic driver differential output
B1 IN/TRIG I Multi-mode Input. I2C selectable as PWM, analog, or trigger. If not used, this pin should be connected to GND
B2 SDA I/O I2C data
B3 GND P Supply ground
C1 SCL I I2C clock
C3 OUT– O Negative haptic-driver differential output
C2 VDD P Supply input (2.5 to 5.5 V). A 0.1-µF capacitor is required.
(1) I = input, O = output, I/O = input and output, P = power

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range, TA = 25°C (unless otherwise noted)
MIN MAX UNIT
Input voltage VDD –0.3 6 V
EN –0.3 VDD + 0.3 V
SDA –0.3 VDD + 0.3 V
SCL –0.3 VDD + 0.3 V
IN/TRIG –0.3 VDD + 0.3 V
Operating free-air temperature, TA –40 85 °C
Operating junction temperature, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V may actually have higher performance.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VDD Supply voltage VDD 2.5 5.5 V
ƒ(PWM) PWM input frequency(1) IN/TRIG Pin 10 250 kHz
ZL Load impedance(1) VDD = 5.2 V 8 Ω
VIL Digital low-level input voltage EN, IN/TRIG, SDA, SCL 0.5 V
VIH Digital high-level input voltage EN, IN/TRIG, SDA, SCL 1.3 V
VI(ANA) Input voltage (analog mode) IN/TRIG 0 1.8 V
ƒ(LRA) LRA Frequency Range(1) 125 300 Hz
(1) Ensured by design. Not production tested.

6.4 Thermal Information

THERMAL METRIC(1) DRV2605 UNIT
YZF (DSBGA)
(9-PINS)
RθJA Junction-to-ambient thermal resistance 145.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 0.9 °C/W
RθJB Junction-to-board thermal resistance 105 °C/W
φJT Junction-to-top characterization parameter 5.1 °C/W
φJB Junction-to-board characterization parameter 103.3 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

TA = 25°C, VDD = 3.6 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(REG) Voltage at the REG pin 1.84 V
IIL Digital low-level input current EN VDD = 5.5 V , VI = 0 V 1 µA
IIH Digital high-level input current IN/TRIG, SDA, SCL
VDD = 5.5 V, VI = VDD 		1 µA
EN
VDD = 5.5 V, VI = VDD 		3.5
VOL Digital low-level output voltage SDAIOL= 4 mA 0.4 V
R(EN-GND) Digital pull-down resistance EN
VDD = 5.5 V , VI = VDD 		2 MΩ
I(SD) Shutdown current V(EN) = 0 V 1.75 4 µA
II(standby) Standby current V(EN) = 1.8 V, STANDBY = 1 1.9 5 µA
IQ Quiescent current V(EN) = 1.8 V, STANDBY = 0, no signal 0.6 1 mA
ZI Input impedance IN/TRIG to V(CM_ANA) 100 kΩ
V(CM_ANA) IN/TRIG common-mode voltage (AC-coupled) AC_COUPLE = 1 0.9 V
ZO(SD) Output impedance in shutdown OUT+ to GND, OUT– to GND 15 kΩ
ZL(th) Load impedance threshold for over-current detection OUT+ to GND, OUT– to GND 4 Ω
I(BAT_AV) Average battery current during operation Duty cycle = 90%, LRA mode, no load 2.5 3.25 mA
Duty cycle = 90%, ERM mode, no load 2.5 3.25

6.6 Timing Requirements

TA = 25°C, VDD = 3.6 V (unless otherwise noted)
MIN NOM MAX UNIT
ƒ(SCL) Frequency at the SCL pin with no wait states 400 kHz
tw(H) Pulse duration, SCL high See Figure 1. 0.6 µs
tw(L) Pulse duration, SCL low 1.3 µs
tsu(1) Setup time, SDA to SCL 100 ns
th(1) Hold time, SCL to SDA 50 ns
t(BUF) Bus free time between stop and start condition See Figure 2. 1.3 µs
tsu(2) Setup time, SCL to start condition 0.6 µs
th(2) Hold time, start condition to SCL 0.6 µs
tsu(3) Setup time, SCL to stop condition 0.6 µs

6.7 Switching Characteristics

TA = 25°C, VDD = 3.6 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t(start) Start-up time Time from the GO bit or external trigger command to output signal 0.7 ms
Time from EN high to output signal (PWM/Analog Modes) 1.5
ƒO(PWM) PWM Output Frequency 19.5 20.5 21.5 kHz
DRV2605 scl_sda_timing_slos854.gifFigure 1. SCL and SDA Timing
DRV2605 i2c_start_stop_timing_slos854.gifFigure 2. Timing for Start and Stop Conditions

6.8 Typical Characteristics

DRV2605 Fig1_ERM_Click_Ext_Edge_Trigger_slos854.png
VDD = 3.6 V ERM open loop
Strong click - 60% External edge trigger
Figure 3. ERM Click with and Without Braking (ROM)
DRV2605 Fig3_ERM_Bounce_Click_Int_Trigger_slos854.png
VDD = 3.6 V ERM open loop
Sequence = 0x01, 0x48 Internal trigger
Figure 5. ERM Click-Bounce (ROM)
DRV2605 Fig5_ERM_RTP_Waveform_slos854.png
VDD = 3.6 V ERM closed loop RTP Mode
Figure 7. ERM Buzz (RTP)
DRV2605 Fig7_Playback_Latency_1ms_slos854.png
VDD = 4.2 V Closed loop No filter
Figure 9. Startup Latency for ERM and LRA
DRV2605 Fig2_LRA_Click_Ext_Level_Trigger_slos854.png
VDD = 3.6 V LRA closed loop
Strong click - 100% External level trigger
Figure 4. LRA Click with Braking (ROM)
DRV2605 Fig4_LRA_Transition_Click_Int_Trigger_slos854.png
VDD = 3.6 V LRA closed loop
Transition click 1 - 100% Internal trigger
Figure 6. LRA Transition-Click (ROM)
DRV2605 Fig6_LRA_PWM_Waveform_slos854.png
VDD = 3.6 V LRA closed loop PWM Mode
Figure 8. LRA Click With and Without Braking (PWM)
DRV2605 SN26704_Fig8_IDD_vs_VDD.pngFigure 10. Supply Current vs Supply Voltage (Full Vibration)

 
Texas Instruments

© Copyright 1995-2025 Texas Instruments Incorporated. All rights reserved.
Submit documentation feedback | IMPORTANT NOTICE | Trademarks | Privacy policy | Cookie policy | Terms of use | Terms of sale