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  • PCM186x 4 通道或 2 通道 192kHz 音频 ADC

    • ZHCSCB3D March   2014  – March 2018 PCM1860 , PCM1861 , PCM1862 , PCM1863 , PCM1864 , PCM1865

      PRODUCTION DATA.  

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  • PCM186x 4 通道或 2 通道 192kHz 音频 ADC
  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化应用示意图
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions: PCM1860 and PCM1861
    2.     Pin Functions: PCM1862, PCM1863, PCM1864, and PCM1865
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: PGA and ADC AC Performance
    6. 7.6  Electrical Characteristics: DC
    7. 7.7  Electrical Characteristics: Digital Filter
    8. 7.8  Timing Requirements: External Clock
    9. 7.9  Timing Requirements: I2C Control Interface
    10. 7.10 Timing Requirements: SPI Control Interface
    11. 7.11 Timing Requirements: Audio Data Interface for Slave Mode
    12. 7.12 Timing Requirements: Audio Data Interface for Master Mode
    13. 7.13 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Features Description
      1. 9.3.1  Analog Front End
      2. 9.3.2  Microphone Support
        1. 9.3.2.1 Mic Bias
      3. 9.3.3  Input Multiplexer (PCM1860 and PCM1861)
      4. 9.3.4  Mixers and Multiplexers (PCM1862, PCM1863, PCM1864, and PCM1865)
      5. 9.3.5  Programmable Gain Amplifier
      6. 9.3.6  Automatic Clipping Suppression
        1. 9.3.6.1 Attenuation Level
        2. 9.3.6.2 Channel Linking
      7. 9.3.7  Zero Crossing Detect
      8. 9.3.8  Digital Inputs
        1. 9.3.8.1 Stereo PCM Sources
        2. 9.3.8.2 Digital PDM Microphones
      9. 9.3.9  Clocks
        1. 9.3.9.1 Description
        2. 9.3.9.2 External Clock-Source Limits
        3. 9.3.9.3 Device Clock Distribution and Generation
        4. 9.3.9.4 Clocking Modes
          1. 9.3.9.4.1 Clock Configuration and Selection for Hardware-Controlled Devices
          2. 9.3.9.4.2 Clock Sources for Software-Controlled Devices
          3. 9.3.9.4.3 Clocking Configuration and Selection for Software-Controlled Devices
            1. 9.3.9.4.3.1 Target Clock Rates for ADC, DSP1 and DSP2
            2. 9.3.9.4.3.2 Configuration of Master Mode
          4. 9.3.9.4.4 BCK Input Slave PLL Mode
          5. 9.3.9.4.5 Software-Controlled Devices ADC Non-Audio MCK PLL Mode
        5. 9.3.9.5 Software-Controlled Devices Manual PLL Calculation
        6. 9.3.9.6 Clock Halt and Error
        7. 9.3.9.7 Clock Halt and Error Detect
        8. 9.3.9.8 Changes in Clock Sources and Sample Rates
      10. 9.3.10 Analog-to-Digital Converters (ADCs)
        1. 9.3.10.1 Main Audio ADCs
        2. 9.3.10.2 Secondary ADC: Energysense and Analog Control
          1. 9.3.10.2.1 Secondary ADC Analog Input Range
          2. 9.3.10.2.2 Frequency Response of the Secondary ADC
        3. 9.3.10.3 Secondary ADC Controlsense DC Level Change Detection
      11. 9.3.11 Energysense
        1. 9.3.11.1 Energysense Signal Loss Flag
        2. 9.3.11.2 Energysense Signal Detect Circuitry
          1. 9.3.11.2.1 Energysense Threshold Levels for Both Signal Loss and Signal Detect
        3. 9.3.11.3 Programming Various Coefficients for Energysense
      12. 9.3.12 Audio Processing
        1. 9.3.12.1 DSP1 Processing Features
          1. 9.3.12.1.1 Digital Decimation Filters
          2. 9.3.12.1.2 Digital PGA
        2. 9.3.12.2 DSP2 Processing Features
          1. 9.3.12.2.1 Digital Mixing Function
      13. 9.3.13 Fade-In and Fade-Out Functions
      14. 9.3.14 Mappable GPIO Pins
      15. 9.3.15 Interrupt Controller
        1. 9.3.15.1 DIN Toggle Detection
        2. 9.3.15.2 Clearing Interrupts
          1. 9.3.15.2.1 Reset Energysense Loss (in Active Mode)
          2. 9.3.15.2.2 Reset Energysense Detect (In Sleep Mode)
          3. 9.3.15.2.3 Reset Controlsense (Active and Sleep Modes)
          4. 9.3.15.2.4 Reset DIN Toggle (In Sleep Mode)
          5. 9.3.15.2.5 Reset PGA Clipping (Active)
      16. 9.3.16 Audio Format Selection and Timing Details
        1. 9.3.16.1 Audio Format Selection
        2. 9.3.16.2 Serial Audio Interface Timing Details
        3. 9.3.16.3 Digital Audio Output 2 Configuration
        4. 9.3.16.4 Time Division Multiplex (TDM Support)
        5. 9.3.16.5 Decimation Filter Select
        6. 9.3.16.6 Serial Audio Data Interface Configuration
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power Mode Descriptions
        1. 9.4.1.1 PCM1860 and PCM1861 Hardware Device Power Down Functions
          1. 9.4.1.1.1 Enter Standby Mode (From Active Mode)
          2. 9.4.1.1.2 Exit From Standby Mode Back to Active
          3. 9.4.1.1.3 Enter or Exit Sleep or Energysense Mode to Active
        2. 9.4.1.2 PCM186x Software Device Power Down Functions
          1. 9.4.1.2.1 Enter or Exit Stand-by Mode
          2. 9.4.1.2.2 Enter Sleep Mode
          3. 9.4.1.2.3 Exit Sleep Mode
        3. 9.4.1.3 Bypassing the Internal LDO to Reduce Power Consumption
    5. 9.5 Programming
      1. 9.5.1 Control
        1. 9.5.1.1 Hardware Control Configuration
        2. 9.5.1.2 Software-Controlled Device Configuration
        3. 9.5.1.3 SPI Interface
          1. 9.5.1.3.1 Register Read and Write Operation
        4. 9.5.1.4 I2C Interface
          1. 9.5.1.4.1 Slave Address
            1. Table 1. I2C Slave Address
          2. 9.5.1.4.2 Packet Protocol
      2. 9.5.2 Current Status Registers
      3. 9.5.3 Real World Software Configuration using Energysense and Controlsense
        1. 9.5.3.1 Active Mode Flow Diagram
        2. 9.5.3.2 Basic Device Configuration
        3. 9.5.3.3 Clear Energysense Interrupt
        4. 9.5.3.4 Update System Settings
        5. 9.5.3.5 Sleep Mode Flow Diagram
        6. 9.5.3.6 Update Controlsense values in Sleep Mode
          1. 9.5.3.6.1 Update System Settings
      4. 9.5.4 Programming and Register Reference
        1. 9.5.4.1 Coefficient Data Formats
      5. 9.5.5 Programming DSP Coefficients on Software-Controlled Devices
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Device Control Method
        1. 10.1.1.1 Hardware Control
        2. 10.1.1.2 Software Control
          1. 10.1.1.2.1 SPI Control
          2. 10.1.1.2.2 I2C Control
      2. 10.1.2 Power-Supply Options
        1. 10.1.2.1 3.3-V AVDD, DVDD, and IOVDD
        2. 10.1.2.2 3.3-V AVDD, DVDD, and 1.8-V IOVDD
      3. 10.1.3 Master Clock Source
      4. 10.1.4 Dual PCM186x TDM Functionality
      5. 10.1.5 Analog Input Configuration
        1. 10.1.5.1 Analog Front-End Circuit For Single-Ended, Line-In Applications
        2. 10.1.5.2 Analog Front-End Circuit for Differential, Line-In Applications
    2. 10.2 Typical Applications
      1. 10.2.1 Stereo Recording Application for PCM186x Hardware-Controlled Devices in Master Mode
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Stereo Recording Application for PCM186x Software-Controlled Devices in Slave PLL Mode with 1.8-V IOVDD
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power-Supply Distribution and Requirements
    2. 11.2 1.8-V Support
    3. 11.3 Brownout Conditions
    4. 11.4 Power-Up Sequence
    5. 11.5 Lowest Power-Down Modes
      1. 11.5.1 Lowest Power In Standby Mode (AVDD = DVDD = IOVDD = 3.3 V)
      2. 11.5.2 Lowest Power in Sleep or Energysense Mode (AVDD = DVDD = IOVDD = 3.3 V)
      3. 11.5.3 Lower Power in Sleep or Energysense Mode (AVDD = DVDD 3.3 V and IOVDD = 1.8 V)
    6. 11.6 Power-On Reset Sequencing Timing Diagram
    7. 11.7 Power Connection Examples
      1. 11.7.1 3.3-V AVDD, DVDD, and IOVDD Example
      2. 11.7.2 3.3-V AVDD, DVDD With 1.8-V IOVDD Example for Lower-Power Applications
    8. 11.8 Fade In
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Grounding and System Partitioning
    2. 12.2 Layout Example
  13. 13Register Maps
    1. 13.1 Register Map Description
    2. 13.2 Register Map Summary
    3. 13.3 Page 0 Registers
      1. 13.3.1  Page 0: Register 1 (address = 0x01) [reset = 0x00]
        1. Table 26. Page 0: Register 1 Field Descriptions
      2. 13.3.2  Page 0: Register 2 (address = 0x02) [reset = 0x00]
        1. Table 27. Page 0: Register 2 Field Descriptions
      3. 13.3.3  Page 0: Register 3 (address = 0x03) [reset = 0x00]
        1. Table 28. Page 0: Register 3 Field Descriptions
      4. 13.3.4  Page 0: Register 4 (address = 0x04) [reset = 0x00]
        1. Table 29. Page 0: Register 4 Field Descriptions
      5. 13.3.5  Page 0: Register 5 (address = 0x05) [reset = 0x86]
        1. Table 30. Page 0: Register 5 Field Descriptions
      6. 13.3.6  Page 0: Register 6 (address = 0x06) [reset = 0x41]
        1. Table 31. Page 0: Register 6 Field Descriptions
      7. 13.3.7  Page 0: Register 7 (address = 0x07) [reset = 0x41]
        1. Table 32. Page 0: Register 7 Field Descriptions
      8. 13.3.8  Page 0: Register 8 (address = 0x08) [reset = 0x42]
        1. Table 33. Page 0: Register 8 Field Descriptions
      9. 13.3.9  Page 0: Register 9 (address = 0x09) [reset = 0x42]
        1. Table 34. Page 0: Register 9 Field Descriptions
      10. 13.3.10 Page 0: Register 10 (address = 0x0A) [reset = 0x00]
        1. Table 35. Page 0: Register 10 Field Descriptions
      11. 13.3.11 Page 0: Register 11 (address = 0x0B) [reset = 0x44]
        1. Table 36. Page 0: Register 11 Field Descriptions
      12. 13.3.12 Page 0: Register 12 (address = 0x0C) [reset = 0x00]
        1. Table 37. Page 0: Register 12 Field Descriptions
      13. 13.3.13 Page 0: Register 13 (address = 0x0D) [reset = 0x00]
        1. Table 38. Page 0: Register 13 Field Descriptions
      14. 13.3.14 Page 0: Register 14 (address = 0x0E) [reset = 0x00]
        1. Table 39. Page 0: Register 14 Field Descriptions
      15. 13.3.15 Page 0: Register 15 (address = 0x0F) [reset = 0x00]
        1. Table 40. Page 0: Register 15 Field Descriptions
      16. 13.3.16 Page 0: Register 16 (address = 0x10) [reset = 0x01]
        1. Table 41. Page 0: Register 16 Field Descriptions
      17. 13.3.17 Page 0: Register 17 (address = 0x11) [reset = 0x20]
        1. Table 42. Page 0: Register 17 Field Descriptions
      18. 13.3.18 Page 0: Register 18 (address = 0x12) [reset = 0x00]
        1. Table 43. Page 0: Register 18 Field Descriptions
      19. 13.3.19 Page 0: Register 19 (address = 0x13) [reset = 0x00]
        1. Table 44. Page 0: Register 19 Field Descriptions
      20. 13.3.20 Page 0: Register 20 (address = 0x14) [reset = 0x00]
        1. Table 45. Page 0: Register 20 Field Descriptions
      21. 13.3.21 Page 0: Register 21 (address = 0x15) [reset = 0x00]
        1. Table 46. Page 0: Register 21 Field Descriptions
      22. 13.3.22 Page 0: Register 22 (address = 0x16) [reset = 0x00]
        1. Table 47. Page 0: Register 22 Field Descriptions
      23. 13.3.23 Page 0: Register 23 (address = 0x17) [reset = 0x00]
        1. Table 48. Page 0: Register 23 Field Descriptions
      24. 13.3.24 Page 0: Register 24 (address = 0x18) [reset = 0x00]
        1. Table 49. Page 0: Register 24 Field Descriptions
      25. 13.3.25 Page 0: Register 25 (address = 0x19) [reset = 0x00]
        1. Table 50. Page 0: Register 25 Field Descriptions
      26. 13.3.26 Page 0: Register 26 (address = 0x1A) [reset = 0x00]
        1. Table 51. Page 0: Register 26 Field Descriptions
      27. 13.3.27 Page 0: Register 27 (address = 0x1B) [reset = 0x00]
        1. Table 52. Page 0: Register 27 Field Descriptions
      28. 13.3.28 Page 0: Register 32 (address = 0x20) [reset = 0x01]
        1. Table 53. Page 0: Register 32 Field Descriptions
      29. 13.3.29 Page 0: Register 33 (address = 0x21) [reset = 0x00]
        1. Table 54. Page 0: Register 33 Field Descriptions
      30. 13.3.30 Page 0: Register 34 (address = 0x22) [reset = 0x01]
        1. Table 55. Page 0: Register 34 Field Descriptions
      31. 13.3.31 Page 0: Register 35 (address = 0x23) [reset = 0x03]
        1. Table 56. Page 0: Register 35 Field Descriptions
      32. 13.3.32 Page 0: Register 37 (address = 0x25) [reset = 0x07]
        1. Table 57. Page 0: Register 37 Field Descriptions
      33. 13.3.33 Page 0: Register 38 (address = 0x26) [reset = 0x03]
        1. Table 58. Page 0: Register 38 Field Descriptions
      34. 13.3.34 Page 0: Register 39 (address = 0x27) [reset = 0x3F]
        1. Table 59. Page 0: Register 39 Field Descriptions
      35. 13.3.35 Page 0: Register 40 (address = 0x28) [reset = 0x01]
        1. Table 60. Page 0: Register 40 Field Descriptions
      36. 13.3.36 Page 0: Register 41 (address = 0x29) [reset = 0x00]
        1. Table 61. Page 0: Register 41 Field Descriptions
      37. 13.3.37 Page 0: Register 42 (address = 0x2A) [reset = 0x00]
        1. Table 62. Page 0: Register 42 Field Descriptions
      38. 13.3.38 Page 0: Register 43 (address = 0x2B) [reset = 0x01]
        1. Table 63. Page 0: Register 43 Field Descriptions
      39. 13.3.39 Page 0: Register 44 (address = 0x2C) [reset = 0x00]
        1. Table 64. Page 0: Register 44 Field Descriptions
      40. 13.3.40 Page 0: Register 45 (address = 0x2D) [reset = 0x00]
        1. Table 65. Page 0: Register 45 Field Descriptions
      41. 13.3.41 Page 0: Register 48 (address = 0x30) [reset = 0x00]
        1. Table 66. Page 0: Register 48 Field Descriptions
      42. 13.3.42 Page 0: Register 49 (address = 0x31) [reset = 0x00]
        1. Table 67. Page 0: Register 49 Field Descriptions
      43. 13.3.43 Page 0: Register 50 (address = 0x32) [reset = 0x00]
        1. Table 68. Page 0: Register 50 Field Descriptions
      44. 13.3.44 Page 0: Register 51 (address = 0x33) [reset = 0x00]
        1. Table 69. Page 0: Register 51 Field Descriptions
      45. 13.3.45 Page 0: Register 52 (address = 0x34) [reset = 0x00]
        1. Table 70. Page 0: Register 52 Field Descriptions
      46. 13.3.46 Page 0: Register 54 (address = 0x36) [reset = 0x01]
        1. Table 71. Page 0: Register 54 Field Descriptions
      47. 13.3.47 Page 0: Register 64 (address = 0x40) [reset =0x80]
        1. Table 72. Page 0: Register 64 Field Descriptions
      48. 13.3.48 Page 0: Register 65 (address = 0x41) [reset = 0x7F]
        1. Table 73. Page 0: Register 65 Field Descriptions
      49. 13.3.49 Page 0: Register 66 (address = 0x42) [reset = 0x00]
        1. Table 74. Page 0: Register 66 Field Descriptions
      50. 13.3.50 Page 0: Register 67 (address = 0x43) [reset = 0x80]
        1. Table 75. Page 0: Register 67 Field Descriptions
      51. 13.3.51 Page 0: Register 68 (address = 0x44) [reset = 0x7F]
        1. Table 76. Page 0: Register 68 Field Descriptions
      52. 13.3.52 Page 0: Register 69 (address = 0x45) [reset = 0x00]
        1. Table 77. Page 0: Register 69 Field Descriptions
      53. 13.3.53 Page 0: Register 70 (address = 0x46) [reset = 0x80]
        1. Table 78. Page 0: Register 70 Field Descriptions
      54. 13.3.54 Page 0: Register 71 (address = 0x47) [reset = 0x7F]
        1. Table 79. Page 0: Register 71 Field Descriptions
      55. 13.3.55 Page 0: Register 72 (address = 0x48) [reset = 0x00]
        1. Table 80. Page 0: Register 72 Field Descriptions
      56. 13.3.56 Page 0: Register 73 (address = 0x49) [reset = 0x80]
        1. Table 81. Page 0: Register 73 Field Descriptions
      57. 13.3.57 Page 0: Register 74 (address = 0x4A) [reset = 0x7F]
        1. Table 82. Page 0: Register 74 Field Descriptions
      58. 13.3.58 Page 0: Register 75 (address = 0x4B) [reset = 0x00]
        1. Table 83. Page 0: Register 75 Field Descriptions
      59. 13.3.59 Page 0: Register 76 (address = 0x4C) [reset = 0x80]
        1. Table 84. Page 0: Register 76 Field Descriptions
      60. 13.3.60 Page 0: Register 77 (address = 0x4D) [reset = 0x7F]
        1. Table 85. Page 0: Register 77 Field Descriptions
      61. 13.3.61 Page 0: Register 78 (address = 0x4E) [reset = 0x00]
        1. Table 86. Page 0: Register 78 Field Descriptions
      62. 13.3.62 Page 0: Register 79 (address = 0x4F) [reset = 0x80]
        1. Table 87. Page 0: Register 79 Field Descriptions
      63. 13.3.63 Page 0: Register 80 (address = 0x50) [reset = 0x7F]
        1. Table 88. Page 0: Register 80 Field Descriptions
      64. 13.3.64 Page 0: Register 81 (address = 0x51) [reset = 0x00]
        1. Table 89. Page 0: Register 81 Field Descriptions
      65. 13.3.65 Page 0: Register 82 (address = 0x52) [reset = 0x80]
        1. Table 90. Page 0: Register 82 Field Descriptions
      66. 13.3.66 Page 0: Register 83 (address = 0x53) [reset = 0x7F]
        1. Table 91. Page 0: Register 83 Field Descriptions
      67. 13.3.67 Page 0: Register 84 (address = 0x54) [reset = 0x00]
        1. Table 92. Page 0: Register 84 Field Descriptions
      68. 13.3.68 Page 0: Register 85 (address = 0x55) [reset = 0x80]
        1. Table 93. Page 0: Register 85 Field Descriptions
      69. 13.3.69 Page 0: Register 86 (address = 0x56) [reset = 0x7F]
        1. Table 94. Page 0: Register 86 Field Descriptions
      70. 13.3.70 Page 0: Register 87 (address = 0x57) [reset = 0x00]
        1. Table 95. Page 0: Register 87 Field Descriptions
      71. 13.3.71 Page 0: Register 88 (address = 0x58) [reset = 0x00]
        1. Table 96. Page 0: Register 88 Field Descriptions
      72. 13.3.72 Page 0: Register 89 (address = 0x59) [reset = 0x00]
        1. Table 97. Page 0: Register 89 Field Descriptions
      73. 13.3.73 Page 0: Register 90 (address = 0x5A) [reset = 0x00]
        1. Table 98. Page 0: Register 90 Field Descriptions
      74. 13.3.74 Page 0: Register 96 (address = 0x60) [reset = 0x01]
        1. Table 99. Page 0: Register 96 Field Descriptions
      75. 13.3.75 Page 0: Register 97 (address = 0x61) [reset = 0x00]
        1. Table 100. Page 0: Register 97 Field Descriptions
      76. 13.3.76 Page 0: Register 98 (address = 0x62) [reset =0x10]
        1. Table 101. Page 0: Register 98 Field Descriptions
      77. 13.3.77 Page 0: Register 112 (address = 0x70) [reset = 0x70]
        1. Table 102. Page 0: Register 112 Field Descriptions
      78. 13.3.78 Page 0: Register 113 (address = 0x71) [reset = 0x10]
        1. Table 103. Page 0: Register 113 Field Descriptions
      79. 13.3.79 Page 0: Register 114 (address = 0x72) [reset = 0x00]
        1. Table 104. Page 0: Register 114 Field Descriptions
      80. 13.3.80 Page 0: Register 115 (address = 0x73) [reset = 0x00]
        1. Table 105. Page 0: Register 115 Field Descriptions
      81. 13.3.81 Page 0: Register 116 (address = 0x74) [reset = 0x00]
        1. Table 106. Page 0: Register 116 Field Descriptions
      82. 13.3.82 Page 0: Register 117 (address = 0x75) [reset = 0x00]
        1. Table 107. Page 0: Register 117 Field Descriptions
      83. 13.3.83 Page 0: Register 120 (address = 0x78) [reset = 0x00]
        1. Table 108. Page 0: Register 120 Field Descriptions
    4. 13.4 Page 1 Registers
      1. 13.4.1  Page 1: Register 1 (address = 0x01) [reset = 0x00]
        1. Table 109. Page 1: Register 1 Field Descriptions
      2. 13.4.2  Page 1: Register 2 (address = 0x02) [reset = 0x00]
        1. Table 110. Page 1: Register 2 Field Descriptions
      3. 13.4.3  Page 1: Register 4 (address = 0x04) [reset = 0x00]
        1. Table 111. Page 1: Register 4 Field Descriptions
      4. 13.4.4  Page 1: Register 5 (address = 0x05) [reset = 0x00]
        1. Table 112. Page 1: Register 5 Field Descriptions
      5. 13.4.5  Page 1: Register 6 (address = 0x06) [reset = 0x00]
        1. Table 113. Page 1: Register 6 Field Descriptions
      6. 13.4.6  Page 1: Register 7 (address = 0x07) [reset = 0x00]
        1. Table 114. Page 1: Register 7 Field Descriptions
      7. 13.4.7  Page 1: Register 8 (address = 0x08) [reset = 0x00]
        1. Table 115. Page 1: Register 8 Field Descriptions
      8. 13.4.8  Page 1: Register 9 (address = 0x09) [reset = 0x00]
        1. Table 116. Page 1: Register 9 Field Descriptions
      9. 13.4.9  Page 1: Register 10 (address = 0x0A) [reset = 0x00]
        1. Table 117. Page 1: Register 10 Field Descriptions
      10. 13.4.10 Page 1: Register 11 (address = 0x0B) [reset = 0x00]
        1. Table 118. Page 1: Register 11 Field Descriptions
    5. 13.5 Page 3 Registers
      1. 13.5.1 Page 3: Register 18 (address = 0x12) [reset =0x40]
        1. Table 119. Page 3: Register 18 Field Descriptions
      2. 13.5.2 Page 3: Register 21 (address = 0x15) [reset = 0x01]
        1. Table 120. Page 3: Register 21 Field Descriptions
    6. 13.6 Page 253 Registers
      1. 13.6.1 Page 253: Register 20 (address = 0x14) [reset = 0x00]
        1. Table 121. Page 253: Register 20 Field Descriptions
  14. 14器件和文档支持
    1. 14.1 文档支持
      1. 14.1.1 相关文档
    2. 14.2 相关链接
    3. 14.3 接收文档更新通知
    4. 14.4 社区资源
    5. 14.5 商标
    6. 14.6 静电放电警告
    7. 14.7 Glossary
  15. 15机械、封装和可订购信息
  16. 重要声明
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DATA SHEET

PCM186x 4 通道或 2 通道 192kHz 音频 ADC

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 高 SNR 性能：
    • 110dB SNR (PCM1861/63/65)
    • 103dB SNR (PCM1860/62/64)
  • ADC 采样率 (fS) = 8kHz 至 192kHz
  • 提供多达四个独立的 ADC 通道
  • 单端 2.1VRMS 满标量程 (FS) 输入
  • 差分 4.2VRMS FS 输入
  • 硬件 (HW) 控制：PCM1860/61
  • 软件 (SW) 控制（I2C 或 SPI）：
    PCM1862/63/64/65
  • 支持多达四个数字麦克风
    （软件控制的器件）
  • 可编程增益放大器 (PGA)：
    • 固定增益：0dB、12dB、32dB
      (PCM1860/61)
    • 软件控制的增益：–12dB 至 +32dB
      (PCM1862/63/64/65)
  • 集成高性能音频 PLL
  • 3.3V 单电源运行
  • 3.3V 时的功耗：
    • < 85mW (PCM1860/61/62/63)
    • < 145mW (PCM1864/65)
  • 用于音频系统唤醒和睡眠的 Energysense 音频内容检测器
  • 主/从音频接口
  • 自动 PGA 削波抑制控制
  • 所有器件之间具有 PCB 封装兼容性

2 应用

  • 家庭影院和电视
  • 语音控制设备
  • 蓝牙®扬声器
  • 麦克风阵列处理器

3 说明

PCM186x 系列（PCM1860、PCM1861、PCM1862、PCM1863、PCM1864 和 PCM1865）音频前端器件采用了新的音频功能集成方法，从而能够轻松地符合欧洲生态设计法规，同时能够以更低的成本实现高性能终端产品。PCM186x 支持 3.3V 单电源运行，并以小封装提供集成的可编程增益放大器 (PGA)；利用该配置，能够以更低的成本实现更小且更智能的产品。

PCM186x 音频前端支持从较小的 mV 级麦克风输入到 2.1VRMS 线路输入的单端输入电平，无需外部电阻分压器。前端混频器 (MIX)、多路复用器 (MUX) 和 PGA 还支持差分 (Diff)、伪差分和单端 (SE) 输入，从而使这些器件成为需要干扰抑制的产品的理想接口。PCM186x 集成了许多可以辅助或替代某些 DSP 功能的系统级功能。

集成的带隙电压基准可提供出色的 PSRR，因此可能无需专用的模拟 3.3V 电源轨。

器件信息(1)

器件型号 封装 封装尺寸（标称值）
PCM186x TSSOP (30) 7.80mm x 4.40mm
  1. 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。

Device Images

简化应用示意图

PCM1860 PCM1861 PCM1862 PCM1863 PCM1864 PCM1865 PCM186x-simplified-application-diagram.gif

4 修订历史记录

Changes from C Revision (August 2014) to D Revision

  • Added 在该数据表中添加了 PCM1860、PCM1862 和 PCM1864 以及相关的内容；这些器件以前位于一个单独的数据表 (SLASE55A) 中Go
  • Changed 为清楚起见，更改了标题Go
  • Changed 更改了特性 项目以包含新的器件Go
  • Added 添加了特性 项目以阐明硬件和软件控制的器件Go
  • Changed 将应用 中的“汽车音响主机”更改成了“语音控制设备”Go
  • Changed 更改了说明 部分文本以阐明 3.3V 电源、集成 PGA 和其他前端 特性Go
  • Changed 更改了简化应用图，以将以前的两个图合并为一个图Go
  • Deleted Typ Performance (3.3-V Supply, –1 dB-FS Input) table; redundant contentGo
  • Changed Device Comparison Table; updated for clarityGo
  • Changed reference voltage output dcoupling point typical value from 0.5 VCC to 0.5 AVDD in VREF pin descriptionGo
  • Changed XO (pin 9) type from "—" to "Digital output" in both Pin Functions tables Go
  • Changed "latch enable" to "word clock" in LRCK pin description Go
  • Changed reference voltage output dcoupling point typical value from 0.5 VCC to 0.5 AVDD in VREF pin description Go
  • Changed "latch enable" to "word clock" in LRCK pin description Go
  • Added operating ambient temperature and junction temperature to Absolute Maximum Ratings tableGo
  • Changed ground voltage differences range from "AGND, DGND" to "AGND to DGND" Go
  • Changed storage temperature max value from 125°C to 150°CGo
  • Changed CDM value from ±1500 V to ±750 VGo
  • Changed "Operating junction temperature range" to "Operating ambient temperature, TA" in Recommended Operating Conditions tableGo
  • Changed Thermal Characteristics table to Thermal Information tableGo
  • Changed Electrical Characteristics: Primary PGA and ADC performance to include secondary ADC performance data, and deleted separate Electrical Characteristics: Secondary ADC Performance table Go
  • Added new table note to clarify test condition at 32-dB PGA gainGo
  • Added min value of 85 dB to input channel signal-to-noise ratio for 32 dBGo
  • Changed input channel signal-to-noise ratio for 32 dB typical value from 93 dB to 90 dBGo
  • Added min value of –76 dB to input channel THD+N, differential input for 32 dB Go
  • Deleted "per input pin" and "out of phase" from full-scale voltage input parameter in Electrical CharacteristicsGo
  • Changed input channel signal-to-noise ratio, single-ended input value for PCM1865 from 110 dB to 106 dB; differential conditions used previouslyGo
  • Changed "Energysense Detection Threshold" to "Default Energysense Signal Detection Threshold" in Electrical Characteristics, Secondary ADC PerformanceGo
  • Changed secondary ADC sampling rate from "same as audio sampling rate" to min of 8 kHz and max of 192 kHzGo
  • Changed Electrical Characteristics, DC conditions from master to slave mode; system clock from 256 × fS to 512 x fSGo
  • Changed POWER section of the Electrical Characteristics, DC; updated section structure for clarityGo
  • Deleted all rows with XTAL as condition; not required for normal operationGo
  • Deleted all rows with Powerdown; not a valid operating mode Go
  • Changed AVDD current typ value for 2-channel, 3.3-V, active mode from 16 mA to 18 mAGo
  • Changed Total power value for 2-channel, 3.3 V, sleep mode from 24 mW to 17.6 mWGo
  • Changed DVDD current for 2-channel, 3.3 V, standby mode from 353 µA to 0.015 mAGo
  • Changed Total power for 2-channel, 3.3 V, standby mode for software device from 0.59 mW to 0.64 mW Go
  • DVDD current for 2-channel, 3.3 V and 1.8 V active mode typ value from 10 µA to 0.015 mAGo
  • Changed Total power for 2-channel, 3.3 V and 1.8 V active mode from 68 mW to 69.2 mWGo
  • Changed Total power for 4-channel, 3.3 V, active mode from 145 mW to 135.3 mW Go
  • Changed Total power for 4-channel, 3.3 V and 1.8 V, active mode from 128 mW to 117.3 mWGo
  • Deleted redundant text "Valid with recommended values on analog rails (AVDD, VREF, and so on)" from PSRRGo
  • Changed "HPF frequency response" to "HPF –3-dB cutoff frequency" in Electrical Characteristics: Digital FilterGo
  • Added maximum BCK frequency rows to Timing Requirements, External Clock tableGo
  • Changed all FFT plot X axes from log scale to linear scaleGo
  • Added Figure 7Go
  • Changed Figure 9Go
  • Deleted previous Figure 11 and Figure 12Go
  • Added Figure 11Go
  • Added Figure 13Go
  • Added Figure 15Go
  • Changed Overview section for clarityGo
  • Deleted Terminology section; moved content to Overview sectionGo
  • Added Feature Description section, and moved existing content hereGo
  • Changed text in Analog Front End section for clarityGo
  • Changed Mic Bias section; internal resistor is a terminating resistorGo
  • Deleted Figure 21 and Figure 22 from Mic Bias sectionGo
  • Added note stating that clocks are required to be running in order to change PGA in the Programmable Gain Amplifier sectionGo
  • Added text to clarify digital PGA update use in Programmable Gain Amplifier sectionGo
  • Changed note to clarify that the full scale moves to 4.2 VRMS when in differential mode at the end of the Programmable Gain Amplifier sectionGo
  • Added new paragraph to end of Stereo PCM Sources sectionGo
  • Changed Figure 33; clock tree updated and correctedGo
  • Added new paragraph to target ADC, DSP1 and DSP2 clock rates in Device Clock Distribution and Generation sectionGo
  • Changed Clock Configuration and Selection section; relevant to hardware-controlled devices onlyGo
  • Added new paragraph regarding register MST_SCK_SRC to Clock Sources for Software-Controlled Devices sectionGo
  • Added note ("In Master Mode on..") to Clock Sources for Software-Controlled Devices sectionGo
  • Changed Table 7; updated descriptions for clarityGo
  • Changed "CLK_DIV_MST_SCK" to "CLK_DIV_SCK_BCK" and "CLK_DIV_MST_BCK" to "CLK_DIV_BCK_LRCK" in Table 7Go
  • Changed Figure 34; clock tree updated and correctedGo
  • Added "Target Clock Rates for ADC, DSP#1 and DSP#2" sectionGo
  • Changed Table 9; corrected PLL values by increasing P and R by 1, and corrected DSP1 clock divider valuesGo
  • Changed Table 10; corrected PLL values by increasing P and R by 1, and corrected DSP1 clock divider valuesGo
  • Changed Table 12; corrected PLL values by increasing P and R by 1, and corrected typo in DSP2 column titleGo
  • Changed Table 13; corrected PLL values by increasing P and R by 1, and corrected typo in DSP2 column titleGo
  • Added text "The clock tree must also be set..." to Software-Controlled Devices ADC Non-Audio MCK PLL Mode sectionGo
  • Changed PLL condition for D = 0000 to show 1 MHz ≤ (PLLCKIN / P) ≤ 20 MHz and 1 ≤ J ≤ 63Go
  • Changed PLL condition for D ≠ 0000 to show 6.667 MHz ≤ (PLLCLKIN / P) ≤ 20 MHz and 4 ≤ J ≤ 11Go
  • Changed register numbers in Software-Controlled Devices Manual PLL Calculation section to align with the register numbers in Table 14Go
  • Changed Clock Halt and Error section; clock error moved to Clocks section, and interrupt capability deletedGo
  • Added Changing Clock Sources and Sample Rates sectionGo
  • Changed Secondary ADC: Energysense and Analog Control section; energysense signal detection not available in active modeGo
  • Changed text from "control signals up to 1.65 V" to "control signals up to 4.3 V" in the Secondary ADC Analog Input Range sectionGo
  • Changed section title from "Secondary ADC DC Level Change Detection" to "Secondary ADC Controlsense DC Level Change Detection"Go
  • Added text to the Secondary ADC Controlsense DC Level Change Detection section; controlsense is available in both active and sleep modesGo
  • Added details to the Secondary ADC Controlsense DC Level Change Detection section regarding how to read simple 8-bit values from the secondary ADCGo
  • Added new second paragraph to Energysense sectionGo
  • Changed paragraph after Figure 38 in Energysense Signal Loss Flag section for clarityGo
  • Changed Digital Decimation Filters section; clarified two different HPFs in the deviceGo
  • Changed text to clarify digital PGA update use in Digital PGA sectionGo
  • Changed Interrupt Controller section; deleted clock error as an interrupt sourceGo
  • Changed text after Figure 44 in Interrupt Controller section; clarified INT pins all have same logic signalGo
  • Added short description in the DIN Toggle Detection sectionGo
  • Added Clearing Interrupts sectionGo
  • Changed Digital Audio Output 2 Configuration section; DOUT2 not available in TDM mode, only for 4-ch devicesGo
  • Added Time Division Multiplex (TDM Support) sectionGo
  • Changed location of timing diagrams to Specifications section, and deleted Interface Timing sectionGo
  • Changed text in Bypassing the Internal LDO to Reduce Power Consumption section to clarify TDM mode with 1.8-V IOVDD operationGo
  • Added text "The I2C control port.." to the I2C Interface sectionGo
  • Changed pin numbers in Table 22 from "15, 16, 14" to "23, 24, 25"Go
  • Added Real World Software Configuration using EnergySense and Controlsense sectionGo
  • Added more detail to Programming DSP Coefficients on Software-Controlled Devices section, and moved to new locationGo
  • Added Dual PCM186x TDM Functionality sectionGo
  • Added new paragraph to end of Analog Front-End Circuit For Single-Ended, Line-In Applications sectionGo
  • Changed 1.8-V Support section; clarified that both IOVDD and LDO must be driven with 1.8 V in 1.8-V modeGo
  • Added Brownout Conditions sectionGo
  • Added test condition to step 3 in Power Up Sequence section; (PLL requires < 250 µs)Go
  • Changed Layout section for clarity Go
  • Deleted old Figure 67, PCM1865 EVM Signal Partitioning; redundant, and same information shown in Figure 74 Go
  • Added Figure 75Go
  • Changed "0xFF" to "0xFE" in last sentence of Register Map Description sectionGo
  • Changed values for register 3, bits 6-0; changed from "RSV" to correct bit names Go
  • Changed bits 4 and 3 from 1 and 0 to RSV, respectively, in register 27Go
  • Changed register 44 (0x2C) from reserved ("RSV") to actual bit namesGo
  • Changed registers 52 and 53 to registers 51 and 52, respectivelyGo
  • Changed TX_WLEN bit option 00 description from "Reserved" to "32-bit" in Page 0, register 11Go
  • Changed GPIO0_FUNC for 001 from "SPI MISO (Out:Default)" to "Digital MIC Input 0 (In)" and for 010 from "RESERVED" to "SPI MISO (Out)" in register 16Go
  • Changed "DPGA" to "APGA" in description column for bits 3, 2, 1, and 0 in register 25Go
  • Changed DIV_NUM default value in page 0, register 33 from "000 0001" to "000 0000"Go
  • Changed names and descriptions of master mode clock dividers in registers 37, 38, and 39 for clarityGo
  • Changed "Divider" to "Multiplier" in R[3:0] description for register 42Go
  • Changed values for R[3:0] from 1, 1/2, 1/3, 1/4, and 1/16 to 1, 2, 3, 4, and 16, respectively Go
  • Changed "Divider" to "Multiplier" in J[5:0] description for register 43 Go
  • Changed "Divider" to "Multiplier" in D_LSB[7:0] description for register 44Go
  • Changed "Divider" to "Multiplier" in D_MSB[5:0] description for register 45Go
  • Changed register 52 to register 51Go
  • Changed register 53 to register 52Go
  • Changed bit 3 from CLKERR to RSV in register 96Go
  • Deleted bit 3 from CLKERR to RSV in register 97Go
  • Changed default values in page 1: register 1 for bits 4, 2, 1, and 0 from "1" to "0", and updated descriptions for clarityGo

Changes from B Revision (March 2014) to C Revision

  • Changed 在整个数据表中将“端子”更改成了“引脚”Go
  • Added 添加了有关可订购产品附录的表注Go
  • Deleted 从“器件信息”表的部件号中删除了封装符号Go
  • Changed 将“-1dBFS 下的 THD+N”更改成了“-1dBFS 下的差分输入”Go
  • Corrected pin numbers in Pin Description tableGo
  • Corrected pin numbers in Pin Description table - pin 11 is LDO and pin 12 is DGNDGo
  • Changed Energysense Accuracy typ from 1dB to 3dBGo
  • Changed Secondary ADC Accuracy from 10 bits to 12 bits Go
  • Added Parameter Measurement Information section Go
  • Added default values for reserved registersGo

Changes from A Revision (March 2014) to B Revision

  • Added 添加了 PCM1861 示例系统图Go
  • Changed 更改了典型性能表Go
  • Updated Page 3 and Page 253 registers Go

Changes from * Revision (March 2014) to A Revision

  • Changed 将“预告信息”更改成了“生产数据”状态Go

5 Device Comparison Table

PART NUMBER PCM1860 PCM1861 PCM1862 PCM1863 PCM1864 PCM1865
Control method H/W I2C or SPI
Differential
SNR performance A weighted data		 103 dB 110 dB 103 dB 110 dB 103 dB 110 dB
Analog front end 2.1 VRMS MUX with fixed PGA gains 2.1 VRMS MUX, MIX, PGA and auxiliary ADC
Simultaneous channel capability 2 2 4
Energysense signal detect Yes (fixed threshold) Yes (programmable threshold)
Energysense signal loss No Yes (programmable threshold)
Controlsense No Yes (programmable threshold)
Interrupt controller No Yes
Digital microphone support No Yes (2) Yes (4)
Clock PLL BCK to generate internal master clock Fully programmable
Lowest power standby mode (1.8-V IOVDD) 7.96 mW 0.22 mW
Digital mixing with digital and analog inputs No Yes
Digital output formats Left-justified, I2S Left-justified, right-justified, I2S, TDM
Interrupt capabilities Energysense signal detect Energysense signal loss and detect, controlsense, post PGA clipping, RX digital toggle

6 Pin Configuration and Functions

DBT Package: PCM1860 and PCM1861
30-Pin TSSOP
Top View

Pin Functions: PCM1860 and PCM1861

PIN TYPE DESCRIPTION
NO. NAME
1 VINL2/VIN1M Analog input Analog input 2, L-channel (or differential M input for input 1)
2 VINR2/VIN2M Analog input Analog input 2, R-channel (or differential M input for input 2)
3 VINL1/VIN1P Analog input Analog input 1, L-channel (or differential P input for input 1)
4 VINR1/VIN2P Analog input Analog input 1, R-channel (or differential P input for input 2)
5 Mic Bias Power Microphone bias output
6 VREF Power Reference voltage output decoupling point (typically, 0.5 AVDD). Connect 1-µF capacitor from this pin to AGND.
7 AGND Power Analog ground
8 AVDD Power Analog power supply (typically, 3.3 V). Connect 0.1-µF and 10-µF capacitors from this pin to AGND.
9 XO Digital output Crystal oscillator output
10 XI Digital input Crystal oscillator input or master clock input (1.8-V CMOS signal)
11 LDO Power Internal low-dropout regulator (LDO) decoupling output, or external 1.8-V input to bypass LDO. Connect 0.1-µF and 10-µF capacitors from this pin to DGND.
12 DGND Power Digital ground
13 DVDD Power Digital power supply (typically, 3.3 V). Connect 0.1-µF and 10-µF capacitors from this pin to DGND.
14 IOVDD Power Power supply for I/O voltages (typically, 3.3 V or 1.8 V).
15 SCKI Digital input CMOS level (3.3 V) master clock input
16 LRCK Digital input/output Audio data word clock (left right clock) input/output(1)
17 BCK Digital input/output Audio data bit clock input/output(1)
18 DOUT Digital output Audio data digital output
19 INT Analog output Interrupt output (for analog input detection). Pull high for active mode, pull low for idle.
20 MD6 Analog input Analog MUX and gain selection using MD6, MD5, and MD2 pins, respectively:
000: SE Ch 1 (VINL1 and VINR1)
001: SE Ch 2 (VINL2 and VINR2)
010: SE Ch 3 (VINL3 and VINR3)
011: SE Ch 4 (VINL4 and VINR4)
100: SE Ch 4 with 12-dB gain
101: SE Ch 4 with 32-dB gain
110: Diff Ch 1 (VIN1P and VIN1M, VIN2P and VIN2M)
111: Diff Ch 2 (VIN3P and VIN3M, VIN4P and VIN4M) with 12-dB gain
21 MD5 Analog input Analog MUX and gain selection (see MD6 pin for description)
22 MD4 Analog input Audio format: high = left-justified, low = I2S
23 MD2 Analog input Analog MUX and gain selection (see MD6 pin for description)
24 MD3 Digital Input Filter select: 0 = FIR decimation filter, 1 = IIR low latency decimation filter
25 MD1 Analog input Audio interface mode selection using MD1 and MD0 pins, respectively:
00: Slave mode, 256 × fS, 384 × fS, 512 × fS autodetect
01: Master mode (512 × fS)
10: Master mode (384 × fS)
11: Master mode (256 × fS)
26 MD0 Analog input Audio interface mode selection (see MD1 pin for description)
27 VINL4/VIN4M Analog input Analog input 4, L-channel (or differential M input for input 4)
28 VINR4/VIN3M Analog input Analog input 4, R-channel (or differential M input for input 3)
29 VINL3/VIN4P Analog input Analog input 3, L-channel (or differential P input for input 4)
30 VINR3/VIN3P Analog input Analog input 3, R-channel (or differential P input for input 3)
(1) Schmitt trigger input with internal pull-down (50 kΩ, typically).
DBT Package: PCM1862, PCM1863, PCM1864, and PCM1865
30-Pin TSSOP
Top View
NOTE: The DMIN2 option for pin 22 is only available on the PCM1864 and PCM1865 devices.

Pin Functions: PCM1862, PCM1863, PCM1864, and PCM1865

PIN TYPE DESCRIPTION
NO. NAME
1 VINL2/VIN1M Analog input Analog input 2, L-channel (or differential M input for input 1)
2 VINR2/VIN2M Analog input Analog input 2, R-channel (or differential M input for input 2)
3 VINL1/VIN1P Analog input Analog input 1, L-channel (or differential P input for input 1)
4 VINR1/VIN2P Analog input Analog input 1, R-channel (or differential P input for input 2)
5 Mic Bias Power Microphone bias output
6 VREF Power Reference voltage output decoupling point (typically, 0.5 AVDD). Connect 1-µF capacitor from this pin to AGND.
7 AGND Power Analog ground
8 AVDD Power Analog power supply (typically, 3.3 V). Connect 0.1-µF and 10-µF capacitors from this pin to AGND.
9 XO Digital output Crystal oscillator output
10 XI Digital input Crystal oscillator input or master clock input (1.8-V CMOS signal)
11 LDO Power Internal LDO decoupling output, or external 1.8-V input to bypass LDO. Connect 0.1-µF and 10-µF capacitors from this pin to DGND.
12 DGND Power Digital ground
13 DVDD Power Digital power supply (typically, 3.3 V). Connect 0.1-µF and 10-µF capacitors from this pin to DGND.
14 IOVDD Power Power supply for I/O voltages (typically, 3.3 V or 1.8 V).
15 SCKI Digital input CMOS level (3.3 V) master clock input
16 LRCK Digital input/output Audio data world clock (left right clock) input/output(1)
17 BCK Digital input/output Audio data bit clock input/output(1)
18 DOUT Analog output Audio data digital output
19 GPIO3/INTC Digital input/output GPIO 3 or interrupt C
20 GPIO2/INTB/DMCLK Digital input/output GPIO 2, interrupt B, or digital microphone clock output
21 GPIO1/INTA/DMIN Digital input/output GPIO 1, interrupt A, or digital microphone input
22 MISO/GPIO0/DMIN2 Digital input/output In SPI mode: master in, slave out
In I2C mode: GPIO0 (or DMIN2 for PCM1864 and PCM1865 only)
23 MOSI/SDA Digital input/output In SPI mode: master out, slave in
In I2C mode: SDA
24 MC/SCL Digital input In SPI mode: serial bit clock
In I2C mode: serial bit clock
25 MS/AD Digital input In SPI mode: chip select
In I2C mode: address pin
26 MD0 Digital input Control method select pin: I2C (tied low or not connected) or SPI (tied high)
27 VINL4/VIN4M Analog input Analog input 4, L-channel (or differential M input for input 4)
28 VINR4/VIN3M Analog input Analog input 4, R-channel (or differential M input for input 3)
29 VINL3/VIN4P Analog input Analog input 3, L-channel (or differential P input for input 4)
30 VINR3/VIN3P Analog input Analog input 3, R-channel (or differential P input for input 3)
(1) Schmitt trigger input with internal pull-down (50 kΩ, typically).

 
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