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  • Using the AM18xx Bootloader

    • SPRABA5D January   2014  – January 2019 AM1802 , AM1802 , AM1806 , AM1806 , AM1808 , AM1808 , AM1810 , AM1810

       

  • CONTENTS
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  • Using the AM18xx Bootloader
  1.   Using the AM18xx Bootloader
    1.     Trademarks
    2. 1  Introduction
    3. 2  Boot Modes
    4. 3  Non-AIS Boot Modes
      1. 3.1 NOR Boot
        1. 3.1.1 Legacy NOR Boot
        2. 3.1.2 Direct NOR Boot
        3. 3.1.3 AIS NOR Boot
      2. 3.2 Host Port Interface (HPI) Boot
      3. 3.3 Emulation Debug Boot
    5. 4  Application Image Script (AIS) Boot
      1. 4.1  Section Load Command (0x58535901)
      2. 4.2  Section Fill Command (0x5853590A)
      3. 4.3  Enable CRC Command (0x58535903)
      4. 4.4  Disable CRC Command (0x58535904)
      5. 4.5  Validate CRC Command (0x58535902)
      6. 4.6  Jump & Close Command (0x58535906)
      7. 4.7  Jump Command (0x58535905)
      8. 4.8  Sequential Read Enable Command (0x58535963)
      9. 4.9  Function Execute Command (0x5853590D)
      10. 4.10 Boot Table Command (0x58535907)
    6. 5  AISgen: Tool to Generate Boot Script (AIS Image)
      1. 5.1 Installation
      2. 5.2 Getting Started
      3. 5.3 Generating AIS
        1. 5.3.1  Boot Mode and Boot Peripheral Setup
        2. 5.3.2  Phase-Locked Loop (PLL) Setup
        3. 5.3.3  Synchronous Dynamic Random Access Memory (SDRAM) Setup
        4. 5.3.4  DDR Setup
        5. 5.3.5  PSC Setup
        6. 5.3.6  Pin Multiplexing Setup
        7. 5.3.7  Application File Selection
        8. 5.3.8  AIS File Selection
        9. 5.3.9  Status and Messages
        10. 5.3.10 Additional AIS Options
          1. 5.3.10.1 CRC
          2. 5.3.10.2 Specifying the Application Entrypoint
        11. 5.3.11 Command Line Usage
    7. 6  Master Boot – Booting From a Slave Memory Device
      1. 6.1 I2C EEPROM Boot
      2. 6.2 SPI EEPROM or Flash Boot
      3. 6.3 NOR Flash Boot
      4. 6.4 NAND Flash Boot
      5. 6.5 MMC/SD Boot
    8. 7  Slave Boot – Booting From an External Master Host
      1. 7.1 About the AIS Interpreter on the Host
      2. 7.2 Start-Word Synchronization (SWS)
      3. 7.3 Ping Op-Code Synchronization (POS)
      4. 7.4 Opcode Synchronization (OS)
    9. 8  UART Boot Host - Using Your PC as a UART Boot Master
      1. 8.1 Getting Started
      2. 8.2 Booting the Device
      3. 8.3 The AIS_Util.cs Source Code
    10. 9  Boot Requirements, Constraints and Default Settings
      1. 9.1 General Comments
      2. 9.2 UART-Boot Modes
      3. 9.3 I2C-Boot Modes
      4. 9.4 SPI-Boot Modes
      5. 9.5 NOR-Boot Modes
      6. 9.6 NAND-Boot Modes
      7. 9.7 MMC/SD-Boot Modes
      8. 9.8 HPI-Boot Modes
    11. 10 References
  2.   A Boot Mode Selection Table
    1.     A.1 Boot Mode Selection Table
  3.   B Details of Supported NAND Devices
    1.     B.1 Details of Supported NAND Devices
  4.   C CRC Computation Algorithm
    1.     C.1 CRC Computation Algorithm
  5.   D Details of Pre-Defined ROM Functions
    1.     D.1 PLL0 Configuration (Index = 0, Argument Count = 2)
    2.     D.2 PLL1 Configuration (Index = 1, Argument Count = 2)
    3.     D.3 Clock Configuration (Index = 2, Argument Count = 1)
      1.      D.3.1 SPI Master Register
      2.      D.3.2 I2C Master Register
      3.      D.3.3 UART Slave Register
      4.      D.3.4 MMC/SD Register
    4.     D.4 mDDR/DDR2 Controller Configuration (Index = 3, Argument Count = 8)
    5.     D.5 EMIFA SDRAM Configuration (Index = 4, Argument Count = 5)
    6.     D.6 EMIFA Async Configuration (Index = 5, Argument Count = 5)
    7.     D.7 PLL and Clock Configuration (Index = 6, Argument Count = 3)
    8.     D.8 Power and Sleep Configuration (PSC) (Index = 7, Argument Count = 1)
    9.     D.9 Pinmux Configuration (Index = 8, Argument Count = 3)
  6.   E ROM Revision History
    1.     E.1 ROMID: D800K002, Silicon Revision 1.0
    2.     E.2 ROMID: D800K004, Silicon Revision 1.1
    3.     E.3 ROMID: D800K006, Silicon Revision 2.0
    4.     E.4 ROMID: D800K008, Silicon Revision 2.1
  7.   Revision History
  8. IMPORTANT NOTICE
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APPLICATION NOTE

Using the AM18xx Bootloader

Using the AM18xx Bootloader

This application report describes various boot mechanisms supported by the AM18xx bootloader read-only memory (ROM) image. Topics covered include the Application Image Script (AIS) boot process, an AISgen tool used to generate boot scripts, protocol for booting the device from an external master device, a UART Boot Host GUI for booting the device from a host PC, and any limitations, default settings, and assumptions made by the bootloader.

Project collateral discussed in this application report can be downloaded from the following URL: http://www.ti.com/lit/zip/spraba5.

Trademarks

Code Composer Studio is a trademark of Texas Instruments.

Windows, Microsoft are registered trademarks of Microsoft Corporation in the United States and.

All other trademarks are the property of their respective owners.

1 Introduction

The AM18xx bootloader resides in the ROM of the device. This document describes the boot protocol used by the bootloader, discusses tools required to generate boot script, and talks about limitations/assumptions for the bootloader.

The AM18xx bootloader has undergone multiple revisions. To check the version of your device, perform the following steps.

  1. Connect to the device in the Code Composer Studio™ software.
  2. Select View → Memory.
  3. Enter the address of the beginning of the ROM, 0xFFFD0000, at the top of the memory window.
  4. Select Character mode at the bottom.

The text d800k008 should appear in the memory window at offset 0x08. For earlier ROM revisions, the text could also appear as d800k002, d800k004, or d800k006. It’s important to know your ROM revision when generating boot images. If you don’t see any of these values in the memory window, this document is not applicable to your device. An abbreviated summary of the ROM boot loader revision history can be found in Section E.

2 Boot Modes

The bootloader supports booting from various memory devices (master mode) as well as from an external master (slave mode). A complete list of the supported boot modes and the configuration of the boot pins to select each one of them can be found in Section A.

All boot modes, except the host port interface (HPI) and two out of the three NOR-boot modes, make use of the AIS for boot purpose. AIS is a Texas Instruments, Inc. proprietary boot script format widely used in TI devices. All boot modes supporting AIS present a unified interface to you. AIS and AISgen, the tool used to generate AIS, will be discussed in detail later in this document.

There are few boot modes that do not make use of AIS and have a special boot interface. For instance,

  • The HPI boot method requires the HPI host to load the application image to the device memory and does not use AIS.
  • There are three methods to boot from a NOR Flash, only one of which uses AIS.

Each of these will be discussed later in the document.

3 Non-AIS Boot Modes

3.1 NOR Boot

NOR (or parallel Flash) boot happens from a NOR Flash device connected to the external memory interface (EMIFA) peripheral on EMA_CS[2]. For this boot mode, the bootloader configures EMIFA for 8-bit access and reads the first word from the NOR Flash. This first word indicates if the NOR Flash should be accessed in 16-bit or 8-bit mode, as well as which boot method to be used. This word is interpreted as shown in Figure 1

The NOR boot configuration word register is shown in Figure 1 and described in Table 1.

Figure 1. NOR Boot Configuration Word
31 12 11 8
Reserved COPY
7 6 5 4 3 1 0
Reserved METHOD Reserved ACCESS

Table 1. NOR Boot Configuration Word Field Descriptions

Bit Field Value Description
31-12 Reserved 0 Reserved
11-8 COPY Length of data to copy from the base of the NOR Flash to the base of the On-chip RAM. This value is used only for the Legacy NOR boot method.
0x00 1 KB
0x01 2 KB
...
0x0E 15 KB
0x0F 16 KB
7-6 Reserved 0 Reserved
5-4 METHOD Boot method
0x0 Legacy NOR boot
0x1 Direct NOR boot
0x2 AIS NOR boot
3-1 Reserved 0 Reserved
0 ACCESS EMIFA access mode
0x0 8-bit access
0x1 16-bit access

If ACCESS == 0x1, bootloader reconfigures EMIFA for 16-bit access before using specified boot METHOD to boot from NOR. The default configuration of the bootloader is for an 8-bit access.

3.1.1 Legacy NOR Boot

When METHOD==0x0, the Legacy NOR boot option will be executed. For Legacy NOR boot, the bootloader copies a block of data, whose size is indicated by the COPY field, from the start of NOR Flash (address 0x60000000) to the start of On-chip RAM (0x80000000). This block of data should hold a secondary bootloader, as shown in Figure 2.

f1_sprab41.gifFigure 2. Structure of Secondary Bootloader for NOR Boot

After copying the required data to On-chip RAM, the bootloader transfers control to the secondary bootloader by branching to address 0x80000004.

3.1.2 Direct NOR Boot

When METHOD==0x1, the Direct NOR boot option will be executed. For Direct NOR boot, the bootloader transfers control directly to the secondary bootloader present in NOR Flash by branching to address 0x60000004. The secondary bootloader is directly executed from there.

3.1.3 AIS NOR Boot

When METHOD==0x2, the AIS NOR boot option will be executed. When booting with this method, the bootloader expects the AIS image to start from address 0x60000004, which is mapped to NOR Flash.

f2_sprab41.gifFigure 3. Placement of AIS for NOR Boot

The AIS boot method is described in detail later in this document.

3.2 Host Port Interface (HPI) Boot

HPI boot happens from the HPI0 peripheral in 16-bit mode. The sequence to boot from HPI is listed below:

  • Bootloader interrupts the host by setting the HINT bit, in the HPIC register, to inform that it is ready and that the host can start loading the application image to device memory.
  • Host acknowledges this interrupt by clearing the HINT bit.
  • Host loads the application image to device memory and writes application entry point to location 0x80000000 in device memory.
  • Host reads back the final word it wrote to device memory to make sure all HPI writes have completed successfully.
  • Host interrupts bootloader by setting DSPINT bit in HPIC register to inform that loading of application image is complete.
  • Bootloader acknowledges host by clearing DSPINT bit.
  • Bootloader reads application entry point (written by host) from address 0x80000000 and branches to it.

3.3 Emulation Debug Boot

The emulation debug boot powers on the device, but does not load or execute any application code. Instead, the ARM falls into an idle loop immediately after the device powers on. An emulation connection (JTAG) must then be established to load program data or perform any other operations.

4 Application Image Script (AIS) Boot

AIS is a format of storing the boot image. Apart from the HPI and two NOR-boot modes described above, all boot modes supported by the AM18xx bootloader use AIS for boot purposes.

AIS is a binary language, accessed in terms of 32-bit (4-byte) words in little endian format. AIS starts with a magic word (0x41504954) and contains a series of AIS commands, which are executed by the bootloader in sequential manner. The Jump & Close (J&C) command marks the end of AIS.

f3_sprab41.gifFigure 4. Structure of AIS

Each AIS command consists of an opcode, optionally followed by one or more arguments, followed by optional data.

f4_sprab41.gifFigure 5. Structure of an AIS Command

The opcode and its arguments are each one word (4 bytes) wide. If the length of data is not a multiple of 4 bytes, it is padded with zeros to make it so.

Knowledge of AIS commands is not required to use the bootloader, but will be discussed in the following sub-sections for completeness. You can skip to the next section if knowledge of AIS commands is not desired.

4.1 Section Load Command (0x58535901)

The user application consists of a number of initialized sections and an application entry point. The Section Load command is used to load each initialized section of the application to device memory.

f5_sprab41.gifFigure 6. Section Load Command

This command takes two arguments: address and size of the section to be loaded, followed by contents of the section (data). If the length of the section content is not a multiple of 4 bytes, appropriate zero padding is added to make it so; zero padding is not reflected in the SIZE argument.

When CRC checking is enabled, the address and size arguments are fed into the CRC update function in that order. After the section is fully loaded to memory, the section data is fed into the CRC update function beginning at the specified address.

4.2 Section Fill Command (0x5853590A)

The Section Fill command is an optimized version of the Section Load command, which is used when a section is completely filled with a pattern (for example, 0x00 or 0xFF).

f6_sprab41.gifFigure 7. Section Fill Command

This command takes four arguments: address and size of the section to be filled, the type of memory access, and the pattern that will fill the memory.

Table 2. Type Word Values for Section Fill Opcode

Value Length of Data Pattern
0 8-bit
1 16-bit
2 32-bit

When CRC checking is enabled, the address, size, type, and pattern arguments are fed into the CRC update function in that order. After the section is completely filled with the specified pattern, the section data is fed into the CRC update function beginning at the specified address.

4.3 Enable CRC Command (0x58535903)

This command enables calculation of the cyclic redundancy check (CRC) over the user-application data loaded using the Section Load/Section Fill commands.

f7_sprab41.gifFigure 8. Enable CRC Command

This command does not take any arguments or data.

 

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