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  • TPS6281x-Q1 Functional Safety FIT Rate, FMD and Pin FMA

    • SLVAEJ5C February   2020  – December 2020 TPS62810-Q1 , TPS62811-Q1 , TPS62812-Q1 , TPS62813-Q1

       

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  • TPS6281x-Q1 Functional Safety FIT Rate, FMD and Pin FMA
  1. 1Overview
  2. 2Functional Safety Failure In Time (FIT) Rates
  3. 3Failure Mode Distribution (FMD)
  4. 4Pin Failure Mode Analysis (Pin FMA)
  5. 5Revision History
  6. IMPORTANT NOTICE
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FUNCTIONAL SAFETY FIT RATE, FMD AND PIN-FMA

TPS6281x-Q1 Functional Safety FIT Rate, FMD and Pin FMA

1 Overview

This document contains information for TPS62810-Q1, TPS62811-Q1, TPS62812-Q1, TPS62813-Q1 (VQFN package) to aid in a functional safety system design. Information provided are:

  • Functional Safety Failure In Time (FIT) rates of the semiconductor component estimated by the application of industry reliability standards.
  • Component failure modes and their distribution (FMD) based on the primary function of the device.
  • Pin failure mode analysis (Pin FMA).

Figure 1-1 shows the device functional block diagram for reference.

GUID-815B3DA4-97D3-4248-8CD9-07AC80A84996-low.gifFigure 1-1 Functional Block Diagram

TPS6281x-Q1 was developed using a quality-managed development process, but was not developed in accordance with the IEC 61508 or ISO 26262 standards.

2 Functional Safety Failure In Time (FIT) Rates

This section provides Functional Safety Failure In Time (FIT) rates for TPS6281x-Q1 based on two different industry-wide used reliability standards:

  • Table 2-1 provides FIT rates based on IEC TR 62380 / ISO 26262 part 11.
  • Table 2-2 provides FIT rates based on the Siemens Norm SN 29500-2.

Table 2-1 Component Failure Rates per IEC TR 62380 / ISO 26262 Part 11
FIT IEC TR 62380 / ISO 26262FIT (Failures Per 109 Hours)
Total Component FIT Rate9
Die FIT Rate5
Package FIT Rate4

The failure rate and mission profile information in Table 2-1 comes from the Reliability data handbook IEC TR 62380 / ISO 26262 part 11:

  • Mission profile motor control
  • Power dissipation: 500 mW
  • Climate type: World-wide table 8
  • Package factor (lambda 3): Table 17b
  • Substrate Material: FR4
  • EOS FIT rate assumed: 0 FIT

Table 2-2 Component Failure Rates per Siemens Norm SN 29500-2
TableCategoryReference FIT RateReference Virtual TJ
5CMOS, BICMOSDigital, analog / mixed25 FIT55 °C

The Reference FIT Rate and Reference Virtual TJ (junction temperature) in Table 2-2 come from the Siemens Norm SN 29500-2 tables 1 through 5. Failure rates under operating conditions are calculated from the reference failure rate and virtual junction temperature using conversion information in SN 29500-2 section 4.

3 Failure Mode Distribution (FMD)

The failure mode distribution estimation for TPS6281x-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity and from best engineering judgment.

The failure modes listed in this section reflect random failure events and do not include failures due to misuse or overstress.

Table 3-1 Die Failure Modes and Distribution
Die Failure ModesFailure Mode Distribution (%)
SW no output35%
SW output not in specification – voltage or timing45%
SW power HS or LS FET stuck on10%
PG false trip or fails to trip5%
Short circuit any two pins5%

4 Pin Failure Mode Analysis (Pin FMA)

This section provides a Failure Mode Analysis (FMA) for the pins of the TPS6281x-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

  • Pin short-circuited to GND (see Table 4-2)
  • Pin open-circuited (see Table 4-3)
  • Pin short-circuited to an adjacent pin (see Table 4-4)
  • Pin short-circuited to VIN (see Table 4-5)

Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects
ClassFailure Effects
APotential device damage that affects functionality
BNo device damage, but loss of functionality
CNo device damage, but performance degradation
DNo device damage, no impact to functionality or performance

Figure 4-1 shows the pin diagram. For a detailed description of the device pins please refer to the 'Pin Configuration and Functions' section in the TPS6281x-Q1 datasheet.

GUID-26AB7A82-0C90-452E-A008-4F4E2F97DE3E-low.gifFigure 4-1 Pin Diagram

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

  • Assumption the device is running in the typical application, please refer to the 'Simplified Schematics' on the 1st page in the TPS62810-Q1 datasheet.

Table 4-2 Pin FMA for Device Pins Short-Circuited to GND
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
MODE/SYNC1Intended functionality.D
VIN2Device does not power up.B
SW3Potential device damage.A
GND4No effect.D
FB5Output voltage regulated to VIN (100% mode).B
SS/TR6Device not functional.B
COMP/FSET7Intended functionality.D
EN8Intended functionality.D
PG9Intended functionality.D
Table 4-3 Pin FMA for Device Pins Open-Circuited
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
MODE/SYNC1Undetermined device operation.B
VIN2Device does not power up.B
SW3Device not functional, open loop operation.B
GND4Device not functional.B
FB5Undetermined output voltage behavior; open loop operation.B
SS/TR6Intended functionality.D
COMP/FSET7Intended functionality.D
EN8Undetermined device operation; device might power up or not.B
PG9Intended functionality.B
Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
Pin NamePin No.Shorted toDescription of Potential Failure Effect(s)Failure Effect Class
MODE/SYNC1PGDevice runs FPWM mode once PG is high impedance.B
FB5SS/TRUndetermined device operation, VOUT spikes up to VINB
SS/TR6COMP/FSETUndetermined device operation.B
EN8PGDevice does not power up.B
Table 4-5 Pin FMA for Device Pins Short-Circuited to VIN
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
MODE/SYNC1Intended functionality: Forced PWM.D
VIN2Intended functionality.D
SW3Potential device damage.A
GND4Device does not power up.B
FB5Potential device damage.A
SS/TR6Intended functionality.D
COMP/FSET7Intended functionality.D
EN8Intended functionality.D
PG9Potential device damage.

A

5 Revision History

Changes from Revision B (September 2020) to Revision C (December 2020)

  • Fixed typo in Section 2 sectionGo
  • Changed "automotive control" to "mission control" in Section 2 sectionGo

Changes from Revision A (April 2020) to Revision B (September 2020)

  • Added Table 2-2 Go

Changes from Revision * (February 2020) to Revision A (April 2020)

  • Added Pin Failure Mode AnalysisGo

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