• Menu
  • Product
  • Email
  • PDF
  • Order now
  • UCC28740-Q1Functional Safety FIT Rate, FMD and Pin FMA

    • SLUAAA8 November   2020 UCC28740-Q1

       

  • CONTENTS
  • SEARCH
  • UCC28740-Q1Functional Safety FIT Rate, FMD and Pin FMA
  1.   Trademarks
  2. 1Overview
  3. 2Functional Safety Failure In Time (FIT) Rates
  4. 3Failure Mode Distribution (FMD)
  5. 4Pin Failure Mode Analysis (Pin FMA)
  6. IMPORTANT NOTICE
search No matches found.
  • Full reading width
    • Full reading width
    • Comfortable reading width
    • Expanded reading width
  • Card for each section
  • Card with all content

 

FUNCTIONAL SAFETY FIT RATE, FMD AND PIN-FMA

UCC28740-Q1Functional Safety FIT Rate, FMD and Pin FMA

Trademarks

All trademarks are the property of their respective owners.

1 Overview

This document contains information for UCC28740-Q1 (SOIC (7) package) to aid in a functional safety system design. Information provided are:

  • Functional Safety Failure In Time (FIT) rates of the semiconductor component estimated by the application of industry reliability standards
  • Component failure modes and their distribution (FMD) based on the primary function of the device
  • Pin failure mode analysis (Pin FMA)

Figure 1-1 shows the device functional block diagram for reference.

GUID-CA9C3EE8-E66C-4F87-8F1E-00797AE1A98A-low.gif Figure 1-1 Functional Block Diagram

UCC28740-Q1 was developed using a quality-managed development process, but was not developed in accordance with the IEC 61508 or ISO 26262 standards.

2 Functional Safety Failure In Time (FIT) Rates

This section provides Functional Safety Failure In Time (FIT) rates for UCC28740-Q1 based on two different industry-wide used reliability standards:

  • Table 2-1 provides FIT rates based on IEC TR 62380 / ISO 26262 part 11
  • Table 2-2 provides FIT rates based on the Siemens Norm SN 29500-2
Table 2-1 Component Failure Rates per IEC TR 62380 / ISO 26262 Part 11
FIT IEC TR 62380 / ISO 26262FIT (Failures Per 109 Hours)
Total Component FIT Rate (50 mW, 100 mW, 150 mW)10, 11, 13
Die FIT Rate (50 mW, 100 mW, 150 mW)3, 4, 5
Package FIT Rate (50 mW, 100 mW, 150 mW)7, 7, 8

The failure rate and mission profile information in Table 2-1 comes from the Reliability data handbook IEC TR 62380 / ISO 26262 part 11:

  • Mission Profile: Motor Control from Table 11
  • Power dissipation: 50 mW, 100 mW, 150 mW
  • Climate type: World-wide Table 8
  • Package factor (lambda 3): Table 17b
  • Substrate Material: FR4
  • EOS FIT rate assumed: 0 FIT
Table 2-2 Component Failure Rates per Siemens Norm SN 29500-2
TableCategoryReference FIT RateReference Virtual TJ
5CMOS, BICMOS
Digital, analog / mixed
25 FIT55°C

The Reference FIT Rate and Reference Virtual TJ (junction temperature) in Table 2-2 come from the Siemens Norm SN 29500-2 tables 1 through 5. Failure rates under operating conditions are calculated from the reference failure rate and virtual junction temperature using conversion information in SN 29500-2 section 4.

3 Failure Mode Distribution (FMD)

The failure mode distribution estimation for UCC28740-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity and from best engineering judgment.

The failure modes listed in this section reflect random failure events and do not include failures due to misuse or overstress.

Table 3-1 Die Failure Modes and Distribution
Die Failure ModesFailure Mode Distribution (%)
DRV stuck high17
DRV stuck low35
Incorrect output regulation22
No effect26

4 Pin Failure Mode Analysis (Pin FMA)

This section provides a Failure Mode Analysis (FMA) for the pins of the UCC28740-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

  • Pin short-circuited to Ground (see Table 4-2)
  • Pin open-circuited (see Table 4-3)
  • Pin short-circuited to an adjacent pin (see Table 4-4)
  • Pin short-circuited to supply (see Table 4-5)

Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects
ClassFailure Effects
APotential device damage that affects functionality
BNo device damage, but loss of functionality
CNo device damage, but performance degradation
DNo device damage, no impact to functionality or performance

Figure 4-1 shows the UCC28740-Q1 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the UCC28740-Q1 data sheet.

GUID-1CE147D2-FA63-4B65-A74D-951D5345348E-low.gif Figure 4-1 Pin Diagram

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

  • The device is connected according to the design procedure application example shown in Figure 19, in UCC28740-Q1 datasheet
  • The supply pin refers to VDD pin
Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
VDD1Device is not functional, system will not startup.B
VS2IC remains in input under voltage protection mode. The output of the flyback converter remains at zero.B
FB3 Device operates at its maximum switching frequency with maximum duty cycle. Output OVP is triggered.B
GND 4 No effect. D
CS 5 When CS pin is shorted to ground before the IC startup, CS pin short protection. The output of the flyback converter remains at zero. B
When CS pin is shorted to ground after the IC in operation, potnetial power stage damange and it might cause IC damage. A
DRV 6 DRV remains low. The output of the flyback converter remains at zero. B
N/A 7
HV 8 The VDD capacitor cannot be trickle charged and the converter will never startup. B
Table 4-3 Pin FMA for Device Pins Open-Circuited
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
VDD1No positive supply applied to device, device is not functional.B
VS 2 IC remains in input under voltage protection mode. The output of the flyback converter remains at zero. B
FB 3 Device operates at its maximum switching frequency with maximum duty cycle. Output OVP is triggered. B
GND 4 Device Damage A
CS 5 CS pin open protection. The output of the Flyback converter remains at zero. B
DRV 6 The output of the Flyback converter remains at zero. B
N/A7
HV8The VDD capacitor cannot be trickle charged. Output of the converter remains at zero volts.B
Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
Pin NamePin No.Shorted toDescription of Potential Failure Effect(s)Failure Effect Class
VDD1VSVS max voltage rating exceeded, device damaged, possible Flyback switch damageA
VS 2 FB FB will not be stable, output voltage will not regulate correctly C
FB 3 GND Device operates at maximum switching frequency with maximum duty cycle. Output over voltage protection will be triggered B
GND 4 N/A
CS 5 DRV CS max voltage rating will be exceeded, device damage, possible Flyback switch damage A
DRV 6 N/A
N/A7N/A
HV8N/A
Table 4-5 Pin FMA for Device Pins Short-Circuited to supply
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
VDD1No Effect.D
VS 2 Pin's maximum voltage rating exceeded, posibble IC damage. A
FB 3 Pin's maximum voltage rating exceeded, posibble IC damage. A
GND 4 No positive supply applied to device. Device is non-functional. B
CS 5 DRV remains low. Possible IC damage. A
DRV 6 DRV remains high. Possible IC damage and Flyback switch damage. A
N/A7
HV8The max rating of VDD will be exceeded, possible device damage and Flyback switch damage.A

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated

 

Texas Instruments

© Copyright 1995-2025 Texas Instruments Incorporated. All rights reserved.
Submit documentation feedback | IMPORTANT NOTICE | Trademarks | Privacy policy | Cookie policy | Terms of use | Terms of sale