• 不借助输出电容器或者任何电容值或类型的电容器即可实现稳定
• 输入电压范围：1.7V 至 5.5V
• 超低压降电压：250mA 时典型值为 40mV
• 无论是否使用可选输出电容器，均可实现出色的负载瞬态响应
• NMOS 拓扑可提供低反向漏电流
• 低噪声：30μV_RMS 典型值（10kHz 至 100kHz）
• 初始精度为 0.5%
• 总体精度（包括线路、负载和温度精度）为 1%
• 关断模式下 I_Q 最大值小于 1μA
• 热关断和指定最小/最大电流限制保护
• 提供了多个输出电压版本：
  • 1.2V 至 5V 固定输出
  • 1.2V 至 5.5V 可调节输出
  • 可提供定制输出

• 便携式和电池供电类设备
• 适用于开关电源的后置稳压
• 噪声敏感电路（如 VCO）
• 适用于 DSP、FPGA、ASIC 和微处理器的负载点调节

TPS732 低压降 (LDO) 稳压器在电压跟随器配置中使用 NMOS 导通晶体管。该拓扑在使用具有低等效串联电阻 (ESR) 的输出电容器时保持稳定，甚至可实现无电容器运行。此器件还提供高反向阻断（低反向电流）和接地引脚电流，该电流在所有输出电流上几乎保持恒定。

TPS732 利用先进的 BiCMOS 工艺实现高精度，同时提供超低压降电压和低接地引脚电流。未启用时，电流消耗小于 1μA，适用于便携式应用。极低的输出噪声（0.1μF C_NR 时为 30μV_RMS）使得此器件非常适合为 VCO 供电。该器件受到热关断和折返电流限制的保护。

针对固定电压版本的典型应用电路

for all voltage versions at T_J = 25°C, V_IN = V_OUT(nom) + 0.5V, I_OUT = 10mA, V_EN = 1.7V, and C_OUT = 0.1μF (unless otherwise noted)

Legacy silicon

Figure 5-1 Load Regulation

Legacy silicon

Figure 5-3 Line Regulation

Legacy silicon

Figure 5-5 Dropout Voltage vs Output Current

Legacy silicon

Figure 5-7 Dropout Voltage vs Temperature

Legacy silicon

Figure 5-9 Output Voltage Accuracy Histogram

Legacy silicon

Figure 5-11 Ground Pin Current vs Output Current

Legacy silicon

Figure 5-13 Ground Pin Current vs Temperature

Legacy silicon

Figure 5-15 Ground Pin Current in Shutdown vs Temperature

Legacy silicon

Figure 5-17 Current Limit vs V_OUT (Foldback)

Legacy silicon

Figure 5-19 Current Limit vs V_IN

Legacy silicon

Figure 5-21 Current Limit vs Temperature

Legacy silicon

Figure 5-23 PSRR (Ripple Rejection) vs Frequency

Legacy silicon

Figure 5-25 PSRR (Ripple Rejection) vs (V_IN – V_OUT)

Legacy silicon

Figure 5-27 Noise Spectral Density C_NR = 0µF

Legacy silicon

Figure 5-29 Noise Spectral Density C_NR = 0.01µF

Legacy silicon

Figure 5-31 RMS Noise Voltage vs C_OUT

Legacy silicon

Figure 5-33 RMS Noise Voltage vs C_NR

Legacy silicon

Figure 5-35 TPS73233 Load Transient Response

Legacy silicon

Figure 5-37 TPS73233 Line Transient Response

Legacy silicon

Figure 5-39 TPS73233 Turn-On Response

Legacy silicon

Figure 5-41 TPS73233 Turn-Off Response

Legacy silicon

Figure 5-43 TPS73233 Power-Up and Power-Down

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Legacy silicon

Figure 5-45 I_ENABLE vs Temperature

Legacy silicon

Figure 5-47 TPS73201 RMS Noise Voltage vs C_FB

Legacy silicon

Figure 5-49 TPS73201 I_FB vs Temperature

Legacy silicon

Figure 5-51 TPS73201 Load Transient, Adjustable Version

Legacy silicon

Figure 5-53 TPS73201 Line Transient, Adjustable Version

New silicon, M3 suffix

Figure 5-2 Load Regulation

New silicon, M3 suffix

Figure 5-4 Line Regulation

New silicon, M3 suffix

Figure 5-6 Dropout Voltage vs Output Current

New silicon, M3 suffix

Figure 5-8 Dropout Voltage vs Temperature

Legacy silicon

Figure 5-10 Output Voltage Drift Histogram

New silicon, M3 suffix

Figure 5-12 Ground Pin Current vs Output Current

New silicon, M3 suffix

Figure 5-14 Ground Pin Current vs Temperature

New silicon, M3 suffix

Figure 5-16 Ground Pin Current in Shutdown vs Temperature

New silicon, M3 suffix

Figure 5-18 Current Limit vs V_OUT (Foldback)

New silicon, M3 suffix

Figure 5-20 Current Limit vs V_IN

New silicon, M3 suffix

Figure 5-22 Current Limit vs Temperature

New silicon, M3 suffix

Figure 5-24 PSRR (Ripple Rejection) vs Frequency

New silicon, M3 suffix

Figure 5-26 PSRR (Ripple Rejection) vs (V_IN – V_OUT)

New silicon, M3 suffix

Figure 5-28 Noise Spectral Density C_NR = 0µF

New silicon, M3 suffix

Figure 5-30 Noise Spectral Density C_NR = 0.01µF

New silicon, M3 suffix

Figure 5-32 RMS Noise Voltage vs C_OUT

New silicon, M3 suffix

Figure 5-34 RMS Noise Voltage vs C_NR

New silicon, M3 suffix

Figure 5-36 TPS73233 Load Transient Response

New silicon, M3 suffix

Figure 5-38 TPS73233 Line Transient Response

New silicon, M3 suffix

Figure 5-40 TPS73233 Turn-On Response

New silicon, M3 suffix

Figure 5-42 TPS73233 Turn-Off Response

New silicon, M3 suffix

Figure 5-44 TPS73233 Power-Up and Power-Down

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New silicon, M3 suffix

Figure 5-46 I_ENABLE vs Temperature

New silicon, M3 suffix

Figure 5-48 TPS73201 RMS Noise Voltage vs C_FB

New silicon, M3 suffix

Figure 5-50 TPS73201 I_FB vs Temperature

New silicon, M3 suffix

Figure 5-52 TPS73201 Load Transient, Adjustable Version

New silicon, M3 suffix

Figure 5-54 TPS73201 Line Transient, Adjustable Version

The TPS732 low-dropout linear regulator operates down to an input voltage of 1.7V and supports output voltages down to 1.2V while sourcing up to 250mA of load current. This linear regulator uses an NMOS pass transistor with an integrated 4MHz charge pump to provide a dropout voltage of less than 150mV at full load current. This unique architecture also permits stable regulation over a wide range of output capacitors. Furthermore, the TPS732 does not require any output capacitor for stability. The increased insensitivity to the output capacitor value and type makes this linear regulator designed for powering a load where the effective capacitance is unknown.

The TPS732 also features a noise-reduction (NR) pin that allows for additional reduction of the output noise. With a noise reduction capacitor of 0.01µF connected from the NR pin to GND, the TPS73215 typical output noise is 12.75µV_RMS. The low noise output featured by the TPS732 makes the device designed for powering VCOs or any other noise-sensitive load.

A precision band-gap reference is used to generate the internal reference voltage, V_REF. This reference is the dominant noise source within the TPS732 and generates approximately 32µV_RMS (10Hz to 100kHz) at the reference output (NR). The regulator control loop gains up the reference noise with the same gain as the reference voltage, so that the noise voltage of the regulator is approximately given by:

Equation 1.

Because the value of V_REF is 1.2V, this relationship reduces to:

Equation 2.

An internal 27kΩ resistor in series with the noise-reduction pin (NR) forms a low-pass filter for the voltage reference when an external noise-reduction capacitor, C_NR, is connected from NR to ground. For C_NR = 10nF, the total noise in the 10Hz to 100kHz bandwidth is reduced by a factor of approximately 3.2, giving the approximate relationship:

Equation 3.

for C_NR = 10nF.

This noise-reduction effect is shown as RMS Noise Voltage vs C_NR (Figure 5-33) in the Typical Characteristics section.

The TPS73201 adjustable version does not have the NR pin available. However, connecting a feedback capacitor, C_FB, from the output to the feedback pin (FB) reduces output noise and improves load transient performance.

The TPS732 uses an internal charge pump to develop an internal supply voltage sufficient to drive the gate of the NMOS pass transistor above V_OUT. The charge pump generates approximately 250μV of switching noise at approximately 4MHz; however, charge-pump noise contribution is negligible at the output of the regulator for most values of I_OUT and C_OUT.

The TPS732 internal current limit helps protect the regulator during fault conditions. Foldback current limit helps to protect the regulator from damage during output short-circuit conditions by reducing current limit when V_OUT drops below 0.5V. See Figure 5-17 in the Typical Characteristics section for a graph of I_OUT vs V_OUT.

From Figure 5-17 approximately –0.2V of V_OUT results in a current limit of 0mA. Therefore, if OUT is forced below –0.2V before EN goes high, the device potentially does not start up. In applications that work with both a positive and negative voltage supply, enable the TPS732 first.

The enable pin (EN) is active high and is compatible with standard TTL-CMOS levels. A V_EN below 0.5V (maximum) turns the regulator off and drops the GND pin current to approximately 10nA. When EN is used to shut down the regulator, all charge is removed from the pass transistor gate. A V_EN above 1.7V (minimum) turns the regulator on and the output ramps back up to a regulated V_OUT (see Figure 5-39).

When shutdown capability is not required, connect EN to V_IN. However, the pass transistor potentially does not discharge using this configuration, causing the pass transistor to be left on (enhanced) for a significant time after V_IN is removed. This scenario results in reverse current flow (if the IN pin is low impedance) and faster ramp times upon power up. In addition, for V_IN ramp times slower than a few milliseconds, the output potentially overshoots upon power up.

Current limit foldback prevents device start-up under some conditions. See the Internal Current Limit section.