UCC2742x-Q1 具有使能端的双路 4A 高速低侧 MOSFET 驱动器
- ZHCSTY3I September 2008 – November 2023 UCC27423-Q1 , UCC27424-Q1 , UCC27425-Q1
  
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UCC2742x-Q1 具有使能端的双路 4A 高速低侧 MOSFET 驱动器

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1 特性

符合汽车应用要求
具有符合 AEC-Q100 标准的下列特性：
- 器件温度等级 1：–40°C 至 +125℃ 环境工作温度范围
- 器件 HBM ESD 分类等级 2
- 器件 CDM ESD 分类等级 C6
业界通用引脚排列
每个驱动器的使能功能
高电流驱动能力：±4A
独特的双极和 CMOS 真正驱动输出级在 MOSFET 米勒阈值提供高电流
与 TTL 和 CMOS 兼容的与电源电压无关的输入
1.8nF 负载时的上升时间和下降时间典型值分别为 20ns 和 15ns
输入下降和上升时的典型传播延迟时间分别为 25ns 和 35ns
4V 至 15V 电源电压
可以并联双输出以获得更高的驱动电流
采用热增强型 MSOP PowerPAD™ 封装
额定温度为 -40°C 至 +125°C

2 应用

开关模式电源
直流/直流转换器
电机控制器
线路驱动器
D 类开关放大器

3 说明

UCC2742x-Q1 系列器件是高速双路 MOSFET 驱动器，可向容性负载提供较大的峰值电流。提供两种标准逻辑选项：双反相驱动器和双同相驱动器。它们采用标准 8 引脚 SOIC (D) 封装。热增强型 8 引脚 PowerPAD 封装 MSOP 封装 (DGN) 大大降低了热阻以改善长期可靠性。

通过使用本身能够更大限度减少击穿电流的设计，这些驱动器可在 MOSFET 开关切换期间，在米勒平坦区域提供最需要的 4A 电流。独特的双极和 MOSFET 混合输出级并联，可在低电源电压下实现高效的拉电流和灌电流。

UCC2742x-Q1 提供使能 (ENBL) 功能，以更好地控制驱动器应用的运行。在引脚 1 和 8 上实现了 ENBA 和 ENBB，之前这些引脚在业界通用引脚排列中未使用。它们内部上拉至 V_DD 电源以实现高电平有效逻辑运行，并且可保持断开连接状态以实现标准运行。

器件信息

器件型号⁽¹⁾	封装	封装尺寸（标称值）
UCC2742x-Q1	SOIC (8)	4.90mm × 3.91mm
UCC2742x-Q1	MSOP 具有 PowerPAD (8)	3.00mm × 3.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。

方框图

4 Device Comparison Table

ORDERABLE PART NUMBER⁽¹⁾	CONFIGURATION
UCC27423QDGNRQ1	Dual Inverting
UCC27424QDGNRQ1	Dual Noninverting
UCC27423QDRQ1	Dual Inverting
UCC27424QDRQ1	Dual Noninverting
UCC27425QDRQ1	One Inverting, One Noninverting

(1) For the most current package and ordering information, see Section 13, or see the TI web site at www.ti.com.

5 Pin Configuration and Functions

Figure 5-1 UCC27423-Q1: D or DGN Package8-Pin SOIC or MSOP With PowerPADDual Inverting, Top View

Figure 5-2 UCC27424-Q1: D or DGN Package8-Pin SOIC or MSOP With PowerPADDual Noninverting, Top View

Figure 5-3 UCC27425-Q1: D Package8-Pin SOICOne Inverting, One Noninverting, Top View

Table 5-1 Pin Functions

PIN		I/O	DESCRIPTION
NO.	NAME	I/O	DESCRIPTION
1	ENBA	I	Enable input for the driver A with logic-compatible threshold and hysteresis. The driver output can be enabled and disabled with this pin. It is internally pulled up to V_DD with 100-kΩ resistor for active high operation. The output state when the device is disabled is low, regardless of the input state.
2	INA	I	Input A. Input signal of the A driver which has logic-compatible threshold and hysteresis. If not used, this input must be tied to either V_DD or GND. It must not be left floating.
3	GND	—	Common ground. This ground must be connected very closely to the source of the power MOSFET which the driver is driving.
4	INB	I	Input B. Input signal of the B driver which has logic-compatible threshold and hysteresis. If not used, this input must be tied to either V_DD or GND. It must not be left floating.
5	OUTB	O	Driver output B. The output stage is capable of providing 4-A drive current to the gate of a power MOSFET.
6	VDD	—	Supply voltage and the power input connection for this device.
7	OUTA	O	Driver output A. The output stage is capable of providing 4-A drive current to the gate of a power MOSFET.
8	ENBB	I	Enable input for the driver B with logic-compatible threshold and hysteresis. The driver output can be enabled and disabled with this pin. It is internally pulled up to V_DD with 100-kΩ resistor for active-high operation. The output state when the device is disabled is low, regardless of the input state.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

			MIN	MAX	UNIT
V_DD	Supply voltage		–0.3	16	V
I_OUT	Output current	DC		0.3	A
I_OUT	Output current	Pulsed, 0.5 µs		4.5	A
V_IN	Input voltage	INA, INB	–5	6⁽³⁾ or (V_DD + 0.3)⁽³⁾	V
V_EN	Enable voltage	ENBA, ENBB	–0.3	6⁽³⁾ or (V_DD + 0.3)⁽³⁾	V
P_D	Power dissipation	T_A = 25°C (D package)		650	mW
P_D	Power dissipation	T_A = 25°C (DGN package)		3	W
T_J	Junction operating temperature		–55	150	°C
T_stg	Storage temperature		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to GND. Currents are positive into, negative out of, the specified terminal.

(3) Whichever is larger.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per AEC Q100-002⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per AEC Q100-011	±1000	V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_DD	Supply voltage	4	15	V
INA	Input voltage	–2	15	V
INB	Input voltage	–2	15	V
ENA	Enable voltage	0	15	V
ENB	Enable voltage	0	15	V
T_J	Operating junction temperature	–40	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		UCC2742x-Q1		UNIT
		D (SOIC)	DGN (MSOP With PowerPAD)
		8 PINS	8 PINS
R_θJA	Junction-to-ambient thermal resistance	112.6	63	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	61.5	53.8	°C/W
R_θJB	Junction-to-board thermal resistance	52.8	35.6	°C/W
ψ_JT	Junction-to-top characterization parameter	15.8	1.9	°C/W
ψ_JB	Junction-to-board characterization parameter	52.3	35.3	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	—	11.9	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

V_DD = 4.5 V to 15 V, T_A = –40°C to 125°C, T_A = T_J (unless otherwise noted)

PARAMETER			TEST CONDITIONS			MIN	TYP	MAX	UNIT
INPUT (INA, INB)
V_IH	Logic 1 input threshold					1.6	2.2	2.5	V
V_IL	Logic 0 input threshold					0.8	1.2	1.5	V
I_IN	Input current		V_IN = 0 V to V_DD			–10	0	10	μA
OUTPUT (OUTA, OUTB)
I_OUT	Output current		V_DD = 14 V⁽¹⁾				4		A
R_OH	Output resistance high		I_OUT = –10 mA, ⁽²⁾				1.2	2.5	Ω
R_OL	Output resistance low		I_OUT = 10 mA, ⁽²⁾				0.7	1.2	Ω
ENABLE (ENBA, ENBB)
V_{IN_H}	High-level input voltage		Low-to-high transition			1.7	2.4	2.9	V
V_{IN_L}	Low-level input voltage		High-to-low transition			1.1	1.8	2.2	V
	Hysteresis					0.15	0.55	0.9	V
R_ENBL	Enable impedance		V_DD = 14 V, ENBL = GND			75	100	145	kΩ
OVERALL
I_DD	Operating current	Static, V_DD = 15 V, ENBA = ENBB = 15 V	UCC27423-Q1	INA = 0 V	INB = 0 V		900	1350	µA
				INA = 0 V	INB = High		750	1100
				INA = High	INB = 0 V		750	1100
				INA = High	INB = High		600	900
			UCC27424-Q1	INA = 0 V	INB = 0 V		300	450
				INA = 0 V	INB = High		750	1100
				INA = High	INB = 0 V		750	1100
				INA = High	INB = High		1200	1800
			UCC27425-Q1	INA = 0 V	INB = 0 V		600	900
				INA = 0 V	INB = High		1050	1600
				INA = High	INB = 0 V		450	700
				INA = High	INB = High		900	1350
		Disabled, V_DD = 15 V, ENBA = ENBB = 0 V	All	INA = 0 V	INB = 0 V		300	450
				INA = 0 V	INB = High		450	700
				INA = High	INB = 0 V		450	700
				INA = High	INB = High		600	900

(1) Parameter not tested in production

(2) Output pullup resistance in this table is a DC measurement that measures resistance of PMOS structure only (not N-channel structure).

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS		TYP	MAX	UNIT
SWITCHING TIME
t_r	Rise time (OUTA, OUTB)	C_LOAD = 1.8 nF⁽¹⁾		20	40	ns
t_f	Fall time (OUTA, OUTB)	C_LOAD = 1.8 nF⁽¹⁾		15	40	ns
t_D1	Delay time, IN rising (IN to OUT)	C_LOAD = 1.8 nF⁽¹⁾		25	50	ns
t_D2	Delay time, IN falling (IN to OUT)	C_LOAD = 1.8 nF⁽¹⁾	UCC27423-Q1, UCC27424-Q1	35	60	ns
t_D2	Delay time, IN falling (IN to OUT)	C_LOAD = 1.8 nF⁽¹⁾	UCC27425-Q1	35	70	ns
ENABLE (ENBA, ENBB)
t_D3	Propagation delay time⁽³⁾	C_LOAD = 1.8 nF⁽¹⁾⁽²⁾		30	60	ns
t_D4	Propagation delay time⁽³⁾	C_LOAD = 1.8 nF⁽¹⁾⁽²⁾		100	150	ns

(1) Specified by design

(2) Not production tested

(3) See Figure 6-2

The 10% and 90% thresholds depict the dynamics of the bipolar output devices that dominate the power MOSFET transition through the Miller regions of operation.

Figure 6-1 Switching Waveforms for (a) Inverting Driver and (b) Noninverting Driver

The 10% and 90% thresholds depict the dynamics of the bipolar output devices that dominate the power MOSFET transition through the Miller regions of operation.

Figure 6-2 Switching Waveform for Enable to Output

6.7 Dissipation Ratings

PACKAGE	θ_JC (°C/W)	θ_JA (°C/W)	POWER RATING T_A = 70°C (mW)⁽¹⁾
D (SOIC-8)	42	84 to 160⁽²⁾	344 to 655⁽²⁾
DGN (MSOP PowerPAD)⁽³⁾	11.9	63	873

(1) 125°C operating junction temperature is used for power rating calculations.

(2) The range of values indicates the effect of the PCB. These values are intended to give the system designer an indication of the best- and worst-case conditions. In general, the system designer should attempt to use larger traces on the PCB, where possible, to spread the heat away form the device more effectively.

(3) The PowerPAD is not directly connected to any leads of the package. However, it is electronically and thermally connected to the substrate which is the ground of the device.

6.8 Typical Characteristics

V_DD = 4.5 V

Figure 6-3 Supply Current vs Frequency

V_DD = 12 V

Figure 6-5 Supply Current vs Frequency

C_LOAD = 2.2 nF

Figure 6-7 Supply Current vs Supply Voltage

Figure 6-9 Supply Current vs Supply Voltage (UCC27423-Q1)

Figure 6-11 Supply Current vs Supply Voltage (UCC27425-Q1)

Figure 6-13 Rise Time vs Supply Voltage

Figure 6-15 Delay Time (t_D1) vs Supply Voltage (UCC27423-Q1)

Figure 6-17 Enable Threshold and Hysteresis vs Temperature

Figure 6-19 Output Behavior vs Supply Voltage (Inverting)

Figure 6-21 Output Behavior vs VDD (Inverting)

Figure 6-23 Output Behavior vs VDD (Noninverting)

Figure 6-25 Output Behavior vs VDD (Noninverting)

Figure 6-27 Input Threshold vs Supply Voltage

V_DD = 8 V

Figure 6-4 Supply Current vs Frequency

V_DD = 15 V

Figure 6-6 Supply Current vs Frequency

C_LOAD = 4.7 nF

Figure 6-8 Supply Current vs Supply Voltage

Figure 6-10 Supply Current vs Supply Voltage (UCC27424-Q1)

Figure 6-12 Rise Time and Fall Time Temperature (UCC27423-Q1)

Figure 6-14 Fall Time vs Supply Voltage

Figure 6-16 Delay Time (t_D2) vs Supply Voltage (UCC27423-Q1)

Figure 6-18 Enable Resistance vs Temperature

Figure 6-20 Output Behavior vs Supply Voltage (Inverting)

Figure 6-22 Output Behavior vs VDD (Inverting)

Figure 6-24 Output Behavior vs VDD (Noninverting)

Figure 6-26 Output Behavior vs VDD (Noninverting)

7 Detailed Description

7.1 Overview

The UCC2742x-Q1 family of high-speed dual MOSFET drivers can deliver large peak currents into capacitive loads. The UCC27423-Q1 offers these standard logic options: dual-inverting drivers, dual noninverting drivers, and one inverting, one noninverting driver. The thermally enhanced 8-pin PowerPAD MSOP package (DGN) drastically lowers the thermal resistance to improve long-term reliability. It is also offered in the standard 8-pin SOIC (D) package. Using a design that inherently minimizes shoot-through current, these drivers deliver 4 A of current where it is needed most at the Miller plateau region during the MOSFET switching transition. A unique Bipolar and MOSFET hybrid output stage in parallel also allows efficient current sourcing and sinking at low supply voltages.