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  • ISOTMP35 具有模拟输出、小于 2 秒响应时间和 500VRMS 工作电压的 ±1.2°C、3kVRMS 隔离温度传感器

    • ZHCSQR7A October   2023  – June 2024 ISOTMP35

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  • ISOTMP35 具有模拟输出、小于 2 秒响应时间和 500VRMS 工作电压的 ±1.2°C、3kVRMS 隔离温度传感器
  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Insulation Specification
    6. 5.6  Power Ratings
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Features Description
      1. 6.3.1 Integrated Isolation Barrier and Thermal Response
      2. 6.3.2 Analog Output
        1. 6.3.2.1 Output Accuracy
        2. 6.3.2.2 Output Voltage Linearity
        3. 6.3.2.3 Drive Capability
        4. 6.3.2.4 Common Mode Transient Immunity (CMTI)
      3. 6.3.3 Thermal Response
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Output Voltage Linearity
      2. 7.1.2 Load Regulation
      3. 7.1.3 Start-Up Settling Time
      4. 7.1.4 Thermal Response
      5. 7.1.5 External Buffer
      6. 7.1.6 ADC Selection and Impact on Accuracy
      7. 7.1.7 Implementation Guidelines
      8. 7.1.8 PSRR
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Insulation Lifetime
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 接收文档更新通知
    3. 8.3 支持资源
    4. 8.4 Trademarks
    5. 8.5 静电放电警告
    6. 8.6 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
  12. 重要声明
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Data Sheet

ISOTMP35 具有模拟输出、小于 2 秒响应时间和 500VRMS 工作电压的 ±1.2°C、3kVRMS 隔离温度传感器

本资源的原文使用英文撰写。 为方便起见,TI 提供了译文;由于翻译过程中可能使用了自动化工具,TI 不保证译文的准确性。 为确认准确性,请务必访问 ti.com 参考最新的英文版本(控制文档)。

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1 特性

  • 稳健可靠的集成隔离栅:
    • 可承受的隔离电压:3000VRMS
    • 隔离工作电压:500VRMS
  • 隔离栅寿命:> 50 年
  • 温度传感器精度
    • ±0.5°C(25°C 时的典型值)
    • 0°C 至 70°C 范围内为 ±1.2°C(最大值)
    • -40°C 至 150°C 范围内为 ±2.5°C(最大值)
  • 工作电源电压范围:2.3V 至 5.5V
  • 正斜率传感器增益:10mV/°C(0°C 下,失调电压为 500mV)
  • 快速热响应:< 2 秒
  • 输出短路保护
  • 低功耗:9µA(典型值)
  • DFQ (SOIC-7) 封装
  • 安全相关认证(计划):
    • 符合 UL 1577 标准且长达 1 分钟的 3kVRMS 隔离

2 应用

  • 交流充电(桩)站
  • 直流快速充电站
  • 具有 48V 输出的机架和服务器 PSU
  • 具有 12V 输出的服务器 PSU
  • 商用直流/直流
  • 商用通信电源整流器
  • 电池备份单元
  • 商用 DIN 轨电源
  • 交流/直流适配器 PSU

3 说明

ISOTMP35 是业界先进的隔离温度传感器 IC,集成了隔离栅,可承受高达 3000VRMS 电压,具有一个模拟温度传感器,可在 –40°C 至 150°C 范围内实现 10mV/°C 的斜率。通过这种集成,可将传感器与高压热源(例如,高压 FET、IGBT 或高压接触器)置于同一位置,而无需昂贵的隔离电路。与通过将传感器放置在较远位置来满足隔离要求的方法相比,直接接触高压热源还可提供更高的精度和更快的热响应。

ISOTMP35 由 2.3V 至 5.5V 的非隔离式电源供电,可轻松集成到高压平面没有子稳压电源的应用中。

集成隔离栅满足 UL 1577 的要求。表面贴装封装(7 引脚 SOIC)可提供从热源到嵌入式热传感器的出色热流,更大限度地降低热质量并提供更精确的热源测量。这降低了对耗时热建模的需求,并通过减少由于制造和组装而产生的机械变化来提高系统设计裕度。

ISOTMP35 AB 类输出驱动器提供强大的 500μA 最高输出,可驱动高达 1000pF 的容性负载,并可直接连接到模数转换器 (ADC) 采样保持输入端。

封装信息
器件型号封装(1)封装尺寸(2)
ISOTMP35DFQ(SOIC,7)4.9mm × 6mm
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附录。
(2) 封装尺寸(长 × 宽)为标称值,并包括引脚(如适用)。
ISOTMP35 功能方框图功能方框图
ISOTMP35 典型应用典型应用

4 Pin Configuration and Functions

Figure 4-1 DFQ Package 7-Pin SOIC Top View
Table 4-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMEDFQ
GND3GGround
NC2

–

No connect
TSENSE5

–

Temperature pin connected to high-voltage heat source
6
7
VDD1PSupply voltage
VOUT4OOutput voltage proportional to temperature
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.

5 Specifications

5.1 Absolute Maximum Ratings

Over free-air temperature range unless otherwise noted(1)
MIN MAX UNIT
Supply voltage VDD –0.3 6 V
Output voltage VOUT –0.3 VDD + 0.3 V
Output current VOUT –30 30 mA
Operating junction temperature, TJ –60 155 °C
Storage temperature, Tstg –65 155 °C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other  conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not  be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

5.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±1000
(1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VDD Supply voltage 2.3 5.5 V
TA Operating ambient temperature –40 150 °C

5.4 Thermal Information

THERMAL METRIC(1) ISOTMP35 UNIT
DFQ (SOIC)
7 PINS
RθJA Junction-to-ambient thermal resistance 116.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 62.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 38.8 °C/W
RθJB Junction-to-board thermal resistance 41.9 °C/W
ψJT Junction-to-top characterization parameter 38.3 °C/W
ψJB Junction-to-board characterization parameter N/A °C/W
MT Thermal Mass 51.0 mJ/°C
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note.

5.5 Insulation Specification

Over free-air temperature range and VDD = 2.3V to 5.5V (unless otherwise noted); Typical specifications are at TA = 25°C and VDD = 3.3V (unless otherwise noted)
PARAMETER TEST CONDITIONS VALUE UNIT
GENERAL
CLR External Clearance(1) Shortest terminal-to-terminal distance through air >4 mm
CPG External Creepage(1) Shortest terminal-to-terminal distance across the package surface >4 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) >17 µm
CTI Comparative tracking index DIN EN 60112; IEC 60112 >400 V
Material Group II
Overvoltage category Rated mains voltage ≤ 150VRMS I-IV
Rated mains voltage ≤ 300VRMS I-III
DIN EN IEC 60747-17 (VDE 0884-17)
VIORM Maximum repetitive peak isolation voltage At AC voltage 707 VPK
VIOWM Maximum-rated isolation working voltage At AC voltage (sine wave) 500 VRMS
At DC voltage 707 VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM, t = 60s (qualification test),
VTEST = 1.2 × VIOTM, t = 1s (100% production test)
4250 VPK
VIMP Maximum impulse voltage(2) Tested in air, 1.2/50-μs waveform per IEC 62368-1 5000  VPK
VIOSM Maximum surge isolation voltage(3) Tested in oil (qualification test),
1.2/50-μs waveform per IEC 62368-1
6500  VPK
qpd Apparent charge(4) Method a, after input/output safety test subgroups 2 and 3,
Vpd(ini) = VIOTM, tini = 60s, Vpd(m) = 1.2 × VIORM, tm = 10s
≤ 5 pC
Method a, after environmental tests subgroup 1,
Vpd(ini) = VIOTM, tini = 60s, Vpd(m) = 1.3 × VIORM, tm = 10s
≤ 5
Method b1, at preconditioning (type test) and routine test,
Vpd(ini) = VIOTM, tini = 1s, Vpd(m) = 1.5 × VIORM, tm = 1s
≤ 5
Method b2, at routine test (100% production)(6),
Vpd(ini) = VIOTM = Vpd(m); tini = tm = 1s
≤ 5
CIO Barrier capacitance,
input to output(5)
VIO = 0.1VPP at 100kHz 1.4  pF
RIO Insulation resistance,
input to output(5)
VIO = 500V at TA = 25°C >1012  Ω
VIO = 500V at 100°C ≤ TA ≤ 125°C >1011 
VIO = 500V at TA = 150°C >109 
Pollution degree 2
Climatic category 55/125/21
UL1577
VISO Withstand isolation voltage VTEST = VISO, t = 60s (qualification);
VTEST = 1.2 × VISO, t = 1s (100% production)
3000 VRMS
(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Take care to maintain the creepage and clearance distance of the board design to make sure that the mounting pads of the isolator on the printed circuit board do not reduce this distance. Creepage and clearance on a printed circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
(2) Testing is carried out in air to determine the surge immunity of the isolation barrier.
(3) Testing is carried out in oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-terminal device.
(6) Either method b1 or b2 is used in production.

 

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