CC2651P3 具有集成式功率放大器的SimpleLink™ 单协议 2.4GHz 无线 MCU
- ZHCSQD6 March 2022 CC2651P3
  
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CC2651P3 具有集成式功率放大器的SimpleLink™ 单协议 2.4GHz 无线 MCU

本资源的原文使用英文撰写。为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

无线微控制器

功能强大的 48 MHz Arm® Cortex®-M4 处理器
352KB 闪存程序存储器
32KB 超低泄漏 SRAM
8KB 缓存 SRAM（也可作为通用 RAM 提供）
可编程无线电包括对 2-(G)FSK、4-(G)FSK、MSK、低功耗 Bluetooth® 5.2、IEEE 802.15.4 PHY 和 MAC 的支持
支持无线升级 (OTA)

低功耗

MCU 功耗：
- 2.91 mA 有源模式，CoreMark®
- 61 μA/MHz（运行 CoreMark 时）
- 0.8 μA 待机模式，RTC，32KB RAM
- 0.1 μA 关断模式，引脚唤醒
无线电功耗：
- RX：6.4 mA
- TX：7.1 mA（在 0 dBm 条件下）
- TX：9.5 mA（在 +5 dBm 条件下）
- TX：22 mA（在 +10 dBm 条件下）
- TX：101 mA（在 +20 dBm 和 7x7 封装条件下）

无线协议支持

高性能无线电

-104 dBm（在 125 kbps 低功耗 Bluetooth® 下）
高达 +20 dBm 的输出功率，具有温度补偿

法规遵从性

适用于符合以下标准的系统：
- ETSI EN 300 328、EN 300 440 类别2 和 3
- FCC CFR47 第 15 部分
- ARIB STD-T66

MCU 外设

数字外设可连接至任何 GPIO
四个 32 位或八个 16 位通用计时器
12 位 ADC、200 ksps、8 通道
8 位 DAC
模拟比较器
UART、SSI、I²C、I²S
实时时钟 (RTC)
集成温度和电池监控器

安全驱动工具

AES 128 位加密加速计
真随机数发生器 (TRNG)
软件开发套件 (SDK) 中提供了其他加密驱动器

开发工具和软件

LP-CC2651P3 开发套件
SimpleLink™ CC13xx 和 CC26xx 软件开发套件 (SDK)
用于简单无线电配置的 SmartRF™ Studio
SysConfig 系统配置工具

工作温度范围

片上降压直流/直流转换器
1.8V 至 3.8V 单电源电压
-40°C 至 +105°C

封装

7mm × 7mm RGZ VQFN48（26 个 GPIO）
5mm × 5mm RKP VQFN40（18 个 GPIO）
符合 RoHS 标准的封装

2 应用

2400 至 2500 MHz ISM 和 SRD 系统，⁽¹⁾
接收带宽低至 4kHz
楼宇自动化
- 楼宇安防系统 – 运动检测器、电子智能锁、门窗传感器、车库门系统、网关
- HVAC – 恒温器、无线环境传感器、HVAC 系统控制器、网关
- 防火安全系统 – 烟雾和热量探测器、火警控制面板 (FACP)
- 视频监控 – IP 网络摄像头
- 升降机和自动扶梯 – 升降机和自动扶梯的电梯主控板
工业运输 – 资产跟踪
工厂自动化和控制
医疗
电子销售终端 (EPOS) – 电子货架标签 (ESL)
通信设备
- 有线网络 – 无线 LAN 或 Wi-Fi 接入点、边缘路由器、小型企业路由器
个人电子产品
- 家庭影院和娱乐 – 智能扬声器、智能显示器、机顶盒
- 可穿戴设备（非医用）– 智能追踪器、智能服装

1. 请参阅射频内核，了解有关支持的协议标准、模块格式和数据速率的更多详细信息。

3 说明

SimpleLink™ CC2651P3 器件是一款单协议 2.4 GHz 无线微控制器 (MCU)，支持以下协议：Zigbee®、低功耗 Bluetooth®5.2、IEEE 802.15.4g、TI 15.4-Stack (2.4 GHz)。CC2651P3 基于 Arm^® Cortex^® M4 主处理器，针对电网基础设施、楼宇自动化、零售自动化、个人电子产品和医疗应用中的低功耗无线通信和高级传感功能进行了优化。

CC2651P3 具有由 Arm® Cortex® M0 驱动的软件定义无线电，支持多个物理层和射频标准。该器件支持在 2360 MHz 至 2500 MHz 频带内运行。CC2651P3 具有高效的内置 PA，支持 +10 dBm TX (21 mA) 和 +20 dBm TX (101 mA)（7x7 封装）。 CC2651P3 接收灵敏度为 -104 dBm（对于 125 kbps 的低功耗 Bluetooth® 编码 PHY）。

在采用 RTC 并保持 32KB RAM 时，CC2651P3 具有 0.8 μA 的低待机电流。

许多客户对产品生命周期的要求为 10 至 15 年或者更久，为了达到这一目标，TI 制定了产品生命周期政策，对产品的寿命和供货连续性作出承诺。

CC2651P3 器件是 SimpleLink™ MCU 平台的一部分，包括 Wi-Fi®、低功耗 Bluetooth®、Thread、Zigbee、Wi-SUN®、Amazon Sidewalk、mioty、Sub-1 GHz MCU 和主机 MCU。 CC2651P3 是可扩展产品系列（闪存为 32KB 至 704KB）的一部分，具有引脚对引脚兼容的封装选项。通用 SimpleLink™ CC13xx 和 CC26xx 软件开发套件 (SDK) 及 SysConfig 系统配置工具支持产品系列中各器件之间的迁移。SDK 随附了丰富的软件栈、应用示例和 SimpleLink™ Academy 培训课程。如需了解更多相关信息，请访问无线连接。

器件信息

器件型号⁽¹⁾	封装	封装尺寸（标称值）
CC2651P31T0RGZR	VQFN (48)	7.00mm × 7.00mm
CC2651P31T0RKPR	VQFN (40)	5.00mm × 5.00mm

(1) 如需所有可用器件的最新器件、封装和订购信息，请参阅Section 12中的“封装选项附录”或访问 TI 网站。

4 功能方框图

图 4-1 CC2651P3 功能方框图

5 Revision History

DATE	REVISION	NOTES
March 2022	*	Initial Release

6 Device Comparison

Device	RADIO SUPPORT											FLASH (KB)	RAM + Cache (KB)	GPIO	PACKAGE SIZE
Device	Sub-1 GHz Prop.	2.4GHz Prop.	Wireless M-Bus	mioty	Wi-SUN®	Sidewalk	Bluetooth® 5.2 LE	ZigBee	Thread	Multiprotocol	+20 dBm PA	FLASH (KB)	RAM + Cache (KB)	GPIO	4 X 4 mm VQFN (32)	5 X 5 mm VQFN (32)	5 X 5 mm VQFN (40)	7 X 7 mm VQFN (48)
CC1310	X		X	X								32-128	16-20 + 8	10-30	X	X		X
CC1311R3	X		X	X								352	32 + 8	22-30			X	X
CC1311P3	X		X	X							X	352	32 + 8	26				X
CC1312R	X		X	X	X							352	80 + 8	30				X
CC1312R7	X		X	X	X	X				X		704	144 + 8	30				X
CC1352R	X	X	X	X	X		X	X	X	X		352	80 + 8	28				X
CC1352P	X	X	X	X	X		X	X	X	X	X	352	80 + 8	26				X
CC1352P7	X	X	X	X	X	X	X	X	X	X	X	704	144 + 8	26				X
CC2640R2F							X					128	20 + 8	10-31	X	X		X
CC2642R							X					352	80 + 8	31				X
CC2642R-Q1							X					352	80 + 8	31				X
CC2651R3		X					X	X				352	32 + 8	23-31			X	X
CC2651P3		X					X	X			X	352	32 + 8	22-26			X	X
CC2652R		X					X	X	X	X		352	80 + 8	31				X
CC2652RB		X					X	X	X	X		352	80 + 8	31				X
CC2652R7		X					X	X	X	X		704	144 + 8	31				X
CC2652P		X					X	X	X	X	X	352	80 + 8	26				X
CC2652P7		X					X	X	X	X	X	704	144 + 8	26				X

7 Pin Configuration and Functions

7.1 Pin Diagram – RGZ Package (Top View)

Figure 7-1 RGZ (7-mm × 7-mm) Pinout, 0.5-mm Pitch (Top View)

The following I/O pins marked in Figure 7-1 in bold have high-drive capabilities:

Pin 10, DIO_5
Pin 11, DIO_6
Pin 12, DIO_7
Pin 24, JTAG_TMSC
Pin 26, DIO_16
Pin 27, DIO_17

The following I/O pins marked in Figure 7-1 in italics have analog capabilities:

Pin 36, DIO_23
Pin 37, DIO_24
Pin 38, DIO_25
Pin 39, DIO_26
Pin 40, DIO_27
Pin 41, DIO_28
Pin 42, DIO_29
Pin 43, DIO_30

7.2 Signal Descriptions – RGZ Package

Table 7-1 Signal Descriptions – RGZ Package

PIN		I/O	TYPE	DESCRIPTION
NAME	NO.	I/O	TYPE	DESCRIPTION
DCDC_SW	33	—	Power	Output from internal DC/DC converter⁽¹⁾
DCOUPL	23	—	Power	For decoupling of internal 1.27 V regulated digital-supply ⁽³⁾
DIO_5	10	I/O	Digital	GPIO, high-drive capability
DIO_6	11	I/O	Digital	GPIO, high-drive capability
DIO_7	12	I/O	Digital	GPIO, high-drive capability
DIO_8	14	I/O	Digital	GPIO
DIO_9	15	I/O	Digital	GPIO
DIO_10	16	I/O	Digital	GPIO
DIO_11	17	I/O	Digital	GPIO
DIO_12	18	I/O	Digital	GPIO
DIO_13	19	I/O	Digital	GPIO
DIO_14	20	I/O	Digital	GPIO
DIO_15	21	I/O	Digital	GPIO
DIO_16	26	I/O	Digital	GPIO, JTAG_TDO, high-drive capability
DIO_17	27	I/O	Digital	GPIO, JTAG_TDI, high-drive capability
DIO_18	28	I/O	Digital	GPIO
DIO_19	29	I/O	Digital	GPIO
DIO_20	30	I/O	Digital	GPIO
DIO_21	31	I/O	Digital	GPIO
DIO_22	32	I/O	Digital	GPIO
DIO_23	36	I/O	Digital or Analog	GPIO, analog capability
DIO_24	37	I/O	Digital or Analog	GPIO, analog capability
DIO_25	38	I/O	Digital or Analog	GPIO, analog capability
DIO_26	39	I/O	Digital or Analog	GPIO, analog capability
DIO_27	40	I/O	Digital or Analog	GPIO, analog capability
DIO_28	41	I/O	Digital or Analog	GPIO, analog capability
DIO_29	42	I/O	Digital or Analog	GPIO, analog capability
DIO_30	43	I/O	Digital or Analog	GPIO, analog capability
EGP	—	—	GND	Ground – exposed ground pad⁽⁵⁾
JTAG_TMSC	24	I/O	Digital	JTAG TMSC, high-drive capability
JTAG_TCKC	25	I	Digital	JTAG TCKC
RESET_N	35	I	Digital	Reset, active low. No internal pullup resistor
RF_P	1	—	RF	Positive RF input signal to LNA during RX Positive RF output signal from PA during TX
RF_N	2	—	RF	Negative RF input signal to LNA during RX Negative RF output signal from PA during TX
RX_TX	7	—	RF	Optional bias pin for the RF LNA
TX_20DBM_P	5	—	RF	Positive high-power TX signal
TX_20DBM_N	6	—	RF	Negative high-power TX signal
VDDR	45	—	Power	Internal supply, must be powered from the internal DC/DC converter or the internal LDO⁽³⁾⁽⁷⁾⁽¹¹⁾
VDDR_RF	48	—	Power	Internal supply, must be powered from the internal DC/DC converter or the internal LDO⁽³⁾⁽⁹⁾⁽¹¹⁾
VDDS	44	—	Power	1.8-V to 3.8-V main chip supply⁽¹⁾
VDDS2	13	—	Power	1.8-V to 3.8-V DIO supply⁽¹⁾
VDDS3	22	—	Power	1.8-V to 3.8-V DIO supply⁽¹⁾
VDDS_DCDC	34	—	Power	1.8-V to 3.8-V DC/DC converter supply
X48M_N	46	—	Analog	48-MHz crystal oscillator pin 1
X48M_P	47	—	Analog	48-MHz crystal oscillator pin 2
X32K_Q1	8	—	Analog	32-kHz crystal oscillator pin 1
X32K_Q2	9	—	Analog	32-kHz crystal oscillator pin 2

(1) For more details, see the device technical reference manual listed in Section 11.3.

(3) Do not supply external circuitry from this pin.

(5) EGP is the only ground connection for the device. Good electrical connection to device ground on printed circuit board (PCB) is imperative for proper device operation.

(7) If internal DC/DC converter is not used, this pin is supplied internally from the main LDO.

(9) If internal DC/DC converter is not used, this pin must be connected to VDDR for supply from the main LDO.

(11) Output from internal DC/DC and LDO is trimmed to 1.68 V.

7.3 Pin Diagram – RKP Package (Top View)

Figure 7-2 RKP (5-mm × 5-mm) Pinout, 0.4-mm Pitch (Top View)

The following I/O pins marked in Figure 7-2 in bold have high-drive capabilities:

Pin 10, DIO_5
Pin 11, DIO_6
Pin 12, DIO_7
Pin 18, JTAG_TMSC
Pin 20, DIO_10
Pin 21, DIO_11

The following I/O pins marked in Figure 7-2 in italics have analog capabilities:

Pin 28, DIO_15
Pin 29, DIO_16
Pin 30, DIO_17
Pin 31, DIO_18
Pin 32, DIO_19
Pin 33, DIO_20
Pin 34, DIO_21
Pin 35, DIO_22

7.4 Signal Descriptions – RKP Package

Table 7-2 Signal Descriptions – RKP Package

PIN		I/O	TYPE	DESCRIPTION
NAME	NO.	I/O	TYPE	DESCRIPTION
DCDC_SW	25	—	Power	Output from internal DC/DC converter⁽¹⁾
DCOUPL	17	—	Power	For decoupling of internal 1.27 V regulated digital-supply ⁽³⁾
DIO_5	10	I/O	Digital	GPIO, high-drive capability
DIO_6	11	I/O	Digital	GPIO, high-drive capability
DIO_7	12	I/O	Digital	GPIO, high-drive capability
DIO_8	14	I/O	Digital	GPIO
DIO_9	15	I/O	Digital	GPIO
DIO_10	20	I/O	Digital	GPIO, JTAG_TDO, high-drive capability
DIO_11	21	I/O	Digital	GPIO, JTAG_TDI, high-drive capability
DIO_12	22	I/O	Digital	GPIO
DIO_13	23	I/O	Digital	GPIO
DIO_14	24	I/O	Digital	GPIO
DIO_15	28	I/O	Digital	GPIO, analog capability
DIO_16	29	I/O	Digital	GPIO, analog capability
DIO_17	30	I/O	Digital	GPIO, analog capability
DIO_18	31	I/O	Digital	GPIO, analog capability
DIO_19	32	I/O	Digital	GPIO, analog capability
DIO_20	33	I/O	Digital	GPIO, analog capability
DIO_21	34	I/O	Digital	GPIO, analog capability
DIO_22	35	I/O	Digital	GPIO, analog capability
EGP	—	—	GND	Ground – exposed ground pad⁽⁵⁾
JTAG_TSMC	18	I/O	Digital	JTAG TMSC, high-drive capability
JTAG_TCKC	19	I	Digital	JTAG TCKC
RESET_N	27	I	Digital	Reset, active low. No internal pullup resistor
RF_P	1	—	RF	Positive RF input signal to LNA during RX Positive RF output signal from PA during TX
RF_N	2	—	RF	Negative RF input signal to LNA during RX Negative RF output signal from PA during TX
RX_TX	7	—	RF	Optional bias pin for the RF LNA
TX_20DBM_P	5	—	RF	Positive high-power TX signal
TX_20DBM_N	6	—	RF	Negative high-power TX signal
VDDR	37	—	Power	Internal supply, must be powered from the internal DC/DC converter or the internal LDO⁽³⁾⁽⁷⁾⁽¹¹⁾
VDDR_RF	40	—	Power	Internal supply, must be powered from the internal DC/DC converter or the internal LDO⁽³⁾⁽⁹⁾⁽¹¹⁾
VDDS	36	—	Power	1.8-V to 3.8-V main chip supply⁽¹⁾
VDDS2	13	—	Power	1.8-V to 3.8-V DIO supply⁽¹⁾
VDDS3	16	—	Power	1.8-V to 3.8-V DIO supply⁽¹⁾
VDDS_DCDC	26	—	Power	1.8-V to 3.8-V DC/DC converter supply
X48M_N	38	—	Analog	48-MHz crystal oscillator pin 1
X48M_P	39	—	Analog	48-MHz crystal oscillator pin 2
X32K_Q1	8	—	Analog	32-kHz crystal oscillator pin 1
X32K_Q2	9	—	Analog	32-kHz crystal oscillator pin 2

(1) For more details, see the device technical reference manual listed in Section 11.3.

(3) Do not supply external circuitry from this pin.

(5) EGP is the only ground connection for the device. Good electrical connection to device ground on printed circuit board (PCB) is imperative for proper device operation.

(7) If internal DC/DC converter is not used, this pin is supplied internally from the main LDO.

(9) If internal DC/DC converter is not used, this pin must be connected to VDDR for supply from the main LDO.

(11) Output from internal DC/DC and LDO is trimmed to 1.68 V.

7.5 Connections for Unused Pins and Modules

Table 7-3 Connections for Unused Pins – RGZ Package

FUNCTION	SIGNAL NAME	PIN NUMBER	ACCEPTABLE PRACTICE⁽¹⁾	PREFERRED PRACTICE⁽¹⁾
GPIO	DIO_n	10–12 14–21 26–32 36–43	NC or GND	NC
32.768-kHz crystal	X32K_Q1	8	NC or GND	NC
32.768-kHz crystal	X32K_Q2	9	NC or GND	NC
No Connects	NC	3–4	NC	NC
DC/DC converter⁽²⁾	DCDC_SW	33	NC	NC
DC/DC converter⁽²⁾	VDDS_DCDC	34	VDDS	VDDS

(1) NC = No connect

(2) When the DC/DC converter is not used, the inductor between DCDC_SW and VDDR can be removed. VDDR and VDDR_RF must still be connected and the 22 uF DCDC capacitor must be kept on the VDDR net.

Table 7-4 Connection for Unused Pins and Modules – RKP Package

FUNCTION	SIGNAL NAME	PIN NUMBER	ACCEPTABLE PRACTICE	PREFERRED PRACTICE
GPIO	DIO_n	10-12 14-15 20-24 28-35	NC or GND	NC
32.768-kHz crystal	X32K_Q1	3	NC or GND	NC
32.768-kHz crystal	X32K_Q2	4	NC or GND	NC
No Connects	NC	3–4	NC	NC
DC/DC converter	DCDC_SW	25	NC	NC
DC/DC converter	VDDS_DCDC	26	VDDS	VDDS

8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾ ⁽²⁾

			MIN	MAX	UNIT
VDDShrefhref	Supply voltage		–0.3	4.1	V
	Voltage on any digital pin(4)⁽⁵⁾		–0.3	VDDS + 0.3, max 4.1	V
	Voltage on crystal oscillator pins, X32K_Q1, X32K_Q2, X48M_N and X48M_P		–0.3	VDDR + 0.3, max 2.25	V
V_in	Voltage on ADC input	Voltage scaling enabled	–0.3	VDDS	V
		Voltage scaling disabled, internal reference	–0.3	1.49
		Voltage scaling disabled, VDDS as reference	–0.3	VDDS / 2.9
	Input level, RF pins (RF_P and RF_N)			5	dBm
T_stg	Storage temperature		–40	150	°C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime

(2) All voltage values are with respect to ground, unless otherwise noted.

(3) VDDS_DCDC, VDDS2 and VDDS3 must be at the same potential as VDDS.

(4) Including analog capable DIOs.

(5) Injection current is not supported on any GPIO pin

(6) Connect VDDR to the external PA bias voltage for +10dBm and VDDS to the external PA bias voltage for +14dBm to +20dBm

8.2 ESD Ratings

				VALUE	UNIT
V_ESD	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS001⁽¹⁾	All pins	±2000	V
V_ESD	Electrostatic discharge	Charged device model (CDM), per JESD22-C101⁽²⁾	All pins	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

	MIN	MAX	UNIT
Operating ambient temperature⁽¹⁾⁽²⁾	–40	105	°C
Operating junction temperature⁽¹⁾⁽²⁾	–40	115	°C
Operating supply voltage (VDDS)	1.8	3.8	V
Rising supply voltage slew rate	0	100	mV/µs
Falling supply voltage slew rate⁽³⁾	0	20	mV/µs

(1) Operation at or near maximum operating temperature for extended durations will result in lifetime reduction.

(2) For thermal resistance characteristics refer to Section 8.8.

(3) For small coin-cell batteries, with high worst-case end-of-life equivalent source resistance, a 22-µF VDDS input capacitor must be used to ensure compliance with this slew rate.

8.4 Power Supply and Modules

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TYP	UNIT
VDDS Power-on-Reset (POR) threshold		1.1 - 1.55	V
VDDS Brown-out Detector (BOD)	Rising threshold	1.77	V
VDDS Brown-out Detector (BOD), before initial boot ⁽¹⁾	Rising threshold	1.70	V
VDDS Brown-out Detector (BOD)	Falling threshold	1.75	V

(1) Brown-out Detector is trimmed at initial boot, value is kept until device is reset by a POR reset or the RESET_N pin