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  • TPSI3050-Q1 具有集成 10-V 栅极电源的汽车类增强型隔离式开关驱动器

    • ZHCSP85D november   2021  – august 2023 TPSI3050-Q1

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  • TPSI3050-Q1 具有集成 10-V 栅极电源的汽车类增强型隔离式开关驱动器
  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristic Curves
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Transmission of the Enable State
      2. 8.3.2 Power Transmission
      3. 8.3.3 Gate Driver
      4. 8.3.4 Modes Overview
      5. 8.3.5 Three-Wire Mode
      6. 8.3.6 Two-Wire Mode
      7. 8.3.7 VDDP, VDDH, and VDDM Undervoltage Lockout (UVLO)
      8. 8.3.8 Power Supply and EN Sequencing
      9. 8.3.9 Thermal Shutdown
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Two-Wire or Three-Wire Mode Selection
        2. 9.2.2.2 Standard Enable, One-Shot Enable
        3. 9.2.2.3 CDIV1, CDIV2 Capacitance
        4. 9.2.2.4 RPXFR Selection
        5. 9.2.2.5 CVDDP Capacitance
        6. 9.2.2.6 Gate Driver Output Resistor
        7. 9.2.2.7 Start-up Time and Recovery Time
        8. 9.2.2.8 Supplying Auxiliary Current, IAUX From VDDM
        9. 9.2.2.9 VDDM Ripple Voltage
      3. 9.2.3 Application Curves
      4. 9.2.4 Insulation Lifetime
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Related Links
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 静电放电警告
    6. 10.6 术语表
  12. 11Mechanical, Packaging, and Orderable Information
  13. 重要声明
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Data Sheet

TPSI3050-Q1 具有集成 10-V 栅极电源的汽车类增强型隔离式开关驱动器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 无需隔离式次级电源
  • 驱动外部功率晶体管或 SCR
  • 5-kVRMS reinforced isolation
  • 具有 1.5/3A 峰值拉电流和灌电流的 10-V 栅极驱动
  • 适用于外部辅助电路的最高 50mW 电源
  • 支持交流或直流开关
  • 支持双线或三线模式
  • 七电平功率传输，电阻可选
  • 功能安全型
    • 可提供用于功能安全系统设计的文档
  • 符合面向汽车应用的 AEC Q-100 标准：
    • 温度等级 1：–40 至 +125°C，TA
  • 安全相关认证
    • 符合 DIN EN IEC 60747-17 (VDE 0884-17) 标准的 7071VPK 增强型隔离
    • 符合 UL 1577 标准且长达 1 分钟的 5kVRMS 隔离

2 应用

  • 固态继电器 (SSR)
  • 电池管理系统
  • 车载充电器
  • 混合动力、电动和动力总成系统
  • 楼宇自动化
  • 工厂自动化和控制

3 说明

TPSI3050-Q1 是一款完全集成的隔离式开关驱动器，与外部电源开关结合使用时，可构成完整的隔离式固态继电器 (SSR)。当标称栅极驱动电压为 10 V、峰值拉电流和灌电流为 1.5/3.0A 时，可以选择多种外部电源开关来满足各种应用需求。TPSI3050-Q1 可通过初级侧电源自行产生次级偏置电源，因此无需隔离式次级电源偏置。而且，TPSI3050-Q1 可以有选择性地向外部配套电路供电，以满足不同的应用需求。

TPSI3050-Q1 根据所需的输入引脚数量，支持两种工作模式。在双线模式（通常用于驱动机械继电器）中，控制开关仅需两个引脚，并支持 6.5V 至 48V 的宽工作电压范围。在三线模式中，由外部提供 3V 至 5.5V 的初级侧电源，并通过独立的使能引脚控制开关。TPSI3050S-Q1 具有可实现开关控制的一次性启用功能，且仅在三线模式下可用。此功能对于驱动 SCR 非常有用，通常只需要一个电流脉冲即可触发。

次级侧可为驱动多种电源开关提供 10 V 的浮动稳压电源轨，无需次级偏置电源。具体用途包括为直流应用驱动单个电源开关，或为交流应用驱动两个背靠背电源开关，以及各种类型的 SCR。TPSI3050-Q1 集成式隔离保护功能非常稳健，与传统机械继电器和光耦合器相比，其可靠性更高、功耗更低，且温度范围更宽。

使用从 PXFR 引脚到 VSSP 的外部电阻器在七个功率等级设置中选择一个，以调节 TPSI3050-Q1 的功率传输。此操作可根据应用需求权衡功率损耗与次级侧功耗。

封装信息
器件型号封装(1)封装尺寸（标称值）
TPSI3050-Q1 SOIC 8 引脚 (DWZ) 7.50mm × 5.85mm
TPSI3050S-Q1
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。
GUID-20201201-CA0I-MVGX-30JK-TVVQGXJQ26T1-low.svgTPSI3050-Q1 简化版原理图

4 Revision History

Changes from Revision C (April 2023) to Revision D (August 2023)

  • Updated Safety-Related Certifications section with associated file and certificate numbersGo

Changes from Revision B (December 2022) to Revision C (April 2023)

  • 删除了 TPSI3050S-Q1 的产品预发布Go
  • 更改了首页格式以与当前 TI 数据表标准保持一致Go
  • Added |ΔVEN/Δt| to Recommended Operating ConditionsGo
  • Added sectionGo
  • Added sectionGo

Changes from Revision A (April 2022) to Revision B (December 2022)

  • 将状态从“预告信息”更改为“量产数据”Go
  • Updated Insulation Specifications to latest standardsGo
  • Updated Figure 6-12,Figure 6-13 Go
  • Updated Figure 6-10,Figure 6-11,Figure 6-8,Figure 6-9 Go
  • Removed tHL_VDDH parameter throughout. Added IQ_VDDH to electrical specification. Go
  • Changed CIN to CVDDP.Go
  • Changed from equal to approximate 0.5-V drop of the VDDH supply. Updated CDIV1, CDIV2 values.Go
  • Updated calculator tool results summary and descriptions.Go
  • Changed CIN to CVDDP.Go
  • Updated IO+ and IO- calculations and values.Go
  • Updated calculator tool results summary and descriptions.Go
  • Updated VDDMripple based on latest revision of calculator tool.Go
  • Added application curves.Go
  • Changed CIN to CVDDP.Go

Changes from Revision * (November 2021) to Revision A (April 2022)

  • 更新了“安全认证”和整个文档的参考资料Go
  • 更新了附带链接的 应用 部分Go
  • 更新了说明部分，表明一次性启用模式仅在
    TPSI3050S-Q1 三线模式下可用    Go
  • Changed name of DUTY pin to PXFR pin throughout the documentGo
  • Updated Insulation Specifications to latest standardsGo
  • Updated Figure 6-10,Figure 6-11,Figure 6-8,Figure 6-9 Go
  • Removed two-wire mode timing, one-shot enable figure because one-shot enable is not supported in
    two-wire mode    Go
  • Updated the description to reflect one-shot enable mode is only available in three-wire mode for
    TPSI3050S-Q1.    Go
  • Changed CIN to CVDDP.Go
  • Removed one-shot enable feature in two-wire mode for TPSI3050S-Q1.Go
  • Updated Table 8-3 to reflect one-shot enable mode is only available in three-wire mode for
    TPSI3050S-Q1.    Go
  • Changed from equal to approximate 0.5-V drop of the VDDH supply.Go
  • Updated calculator tool results summary and descriptions.Go
  • Changed CIN to CVDDP.Go
  • Updated IO+ and IO- calculations and values.Go
  • Updated calculator tool results summary and descriptions.Go
  • Updated Figure 9-14, Figure 9-15, Figure 9-16.Go

5 Pin Configuration and Functions

GUID-20201201-CA0I-GFBZ-4M3G-7W82T4BSNG4M-low.svg Figure 5-1 TPSI3050-Q1, TPSI3050S-Q1 8-Pin SOIC Top View
Table 5-1 Pin Functions
PIN I/O TYPE(1) DESCRIPTION
NO. NAME
1 EN I — Active high driver enable
2 PXFR I — Power transfer can be adjusted by selecting one of seven power level settings using an external resistor from the PXFR pin to VSSP. In three-wire mode, a given resistor setting sets the duty cycle of the power converter (see Table 8-1) and hence the amount of power transferred. In two-wire mode, a given resistor setting adjusts the current limit of the EN pin (see Table 8-2) and hence the amount of power transferred.
3 VDDP — P Power supply for primary side
4 VSSP — GND Ground supply for primary side
5 VSSS — GND Ground supply for secondary side
6 VDDM — P Generated mid supply
7 VDDH — P Generated high supply
8 VDRV O — Active high driver output
(1) P = power, GND = ground, NC = no connect

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER(1) MIN MAX UNIT
Primary Side Supply(2) VDDP –0.3 6 V
EN –0.3 60 V
PXFR –0.3 60 V
Secondary Side Supply(3) VDRV –0.3 12 V
VDDH –0.3 12 V
VDDM –0.3 6 V
VDDH – VDDM –0.3 6 V
Junction temperature, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to VSSP.
(3) All voltage values are with respect to VSSS.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1)
HBM ESD classification level 2		 ±2000 V
Charged device model (CDM), per AEC Q100-011
CDM ESD classification level C4B		 Corner pins (1, 4, 5, and 8) ±750
Other pins ±500
(1) AEC Q100-002 indicates that HBM stressing must be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDDP Primary side supply voltage three-wire mode(1) 3.0 5.5 V
EN Enable in two-wire mode(1) 0 48.0 V
Enable in three-wire mode(1) 0 5.5 V
PXFR Power transfer control(1) 0 5.5 V
CVDDP Decoupling capacitance on VDDP and VSSP, two-wire mode(3) 220 330 nF
Decoupling capacitance on VDDP and VSSP, three-wire mode(3) 0.22 20 µF
CDIV1(2) Decoupling capacitance across VDDH and VDDM(3) 0.003 40 µF
CDIV2(2) Decoupling capacitance across VDDM and VSSS(3) 0.003 40 µF
TA Ambient operating temperature –40 125 °C
TJ Operating junction temperature –40 150 °C
|ΔVEN/Δt| EN rise and fall rates, two-wire mode. 65 V/ms
(1) All voltage values are with respect to VSSP.
(2) CDIV2 ≥ CDIV1. CDIV1 and CDIV2 should be of same type and tolerance.
(3) All capacitance values are absolute. Derating should be applied where necessary.

6.4 Thermal Information

THERMAL METRIC(1) DEVICE UNIT
DWZ(SOIC)
8 PINS
RϴJA Junction-to-ambient thermal resistance 89.3 °C/W
RϴJC(top) Junction-to-case (top) thermal resistance 40.3 °C/W
RΘJB Junction-to-board thermal resistance 45.2 °C/W
ψJT Junction-to-top characterization parameter 10.3 °C/W
ΨJB Junction-to-board characterization parameter 44.4 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Power Ratings

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PD Maximum power dissipation, VDDP. VVDDP = 5 V,
RPXFR = 20 kΩ, three-wire mode,
CVDRV = 100 pF,
CDIV1 = CDIV2 = 100 nF,
fEN = 1-kHz square wave, VEN = 5 V peak to peak.		 250 mW
Maximum power dissipation, EN. RPXFR = 20 kΩ, two-wire mode,
CVDRV = 100 pF,
CDIV1 = CDIV2 = 100 nF,
fEN = 1-kHz square wave, VEN = 48 V peak to peak.		 350 mW

6.6 Insulation Specifications

PARAMETER TEST CONDITIONS SPECIFICATION UNIT
GENERAL
CLR External clearance(1) Shortest terminal-to-terminal distance through air ≥ 8.5 mm
CPG External Creepage(1) Shortest terminal-to-terminal distance across the package surface ≥ 8.5 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) ≥ 120 µm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 ≥ 600 V
Material Group According to IEC 60664-1 I
Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 600 VRMS I-IV
Rated mains voltage ≤ 1000 VRMS I-III
DIN EN IEC 60747-17 (VDE 0884-17)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 1414 VPK
VIOWM Maximum isolation working voltage AC voltage (sine wave) 1000 VRMS
DC voltage 1414 VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM; t = 60 s (qualification test) 7070 VPK
VTEST = 1.2 × VIOTM; t = 1 s (100% production test) 8484 VPK
VIMP Maximum impulse voltage(3) Tested in air;
1.2/50-µs waveform per IEC 62638-1		 9230 VPK
VIOSM Maximum surge isolation voltage(3) Tested in oil (qualification test);
1.2/50-µs waveform per IEC 62638-1		 12000 VPK
qpd Apparent charge(4) Method a: After input-output safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM, tm = 10 s.		 ≤ 5 pC
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM, tm = 10 s.		 ≤ 5
Method b1: At routine test (100% production test) and preconditioning (type test), Vini = VIOTM, tini = 1 s;
Vpd(m) = 1.875 × VIORM, tm = 1 s.		 ≤ 5
CIO Barrier capacitance, input to output(5) VIO = 0.4 × sin (2πft), f = 1 MHz 3 pF
RIO Insulation resistance, input to output(5) VIO = 500 V, TA = 25°C > 1012 Ω
VIO = 500 V, 100°C ≤ TA ≤ 125°C > 1011
VIO = 500 V at TS = 150°C > 109
Pollution degree 2
Climatic category 40/125/21
UL 1577
VISO Withstand isolation voltage VTEST = VISO = 5000 VRMS, t = 60 s (qualification test), VTEST = 1.2 × VISO = 6000 VRMS, t = 1 s (100% production test) 5000 VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed-circuit board are used to help increase these specifications.
(2) Testing is carried out in air to determine the intrinsic surge immunity of the package.
(3) Testing is carried out in oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.

6.7 Safety-Related Certifications

VDE UL
Certified according to DIN EN IEC 60747-17 (VDE 0884-17) Recognized under UL 1577 Component Recognition Program
Reinforced insulation; Maximum transient isolation voltage, 7071 VPK; Maximum repetitive peak isolation voltage, 1414 VPK; Maximum surge isolation voltage, 12000 VPK Single protection, 5000 VRMS
Certificate number: 40040142 File number: UL-US-2300613-0

6.8 Safety Limiting Values

PARAMETER(1)(2) TEST CONDITIONS MIN TYP MAX UNIT
IS Safety input, output, or supply current RθJA = 89.3°C/W, VVDDP = 5.5 V,
TJ = 150°C, TA = 25°C,
three-wire mode.		 254 mA
RθJA = 89.3°C/W, VEN = 24 V,
TJ = 150°C, TA = 25°C,
two-wire mode.		 58
RθJA = 89.3°C/W, VEN = 48 V,
TJ = 150°C, TA = 25°C,
two-wire mode.		 29
PS Safety input, output, or total power RθJA = 89.3°C/W,
TJ = 150°C, TA = 25°C.		 1.4 W
TS Maximum safety temperature 150 °C
(1) Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures.
(2) The safety-limiting constraint is the maximum junction temperature specified in the data sheet. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.

6.9 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted). Typicals at TA = 25℃. CVDDP = 220 nF, CDIV1 = CDIV2 = 3.3 nF, CVDRV = 100 pF, RPXFR = 7.32 kΩ ± 1% 
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
COMMON
VVDDP_UV_R VDDP undervoltage threshold rising VDDP rising 2.50 2.70 2.90 V
VVDDP_UV_F VDDP undervoltage threshold falling VDDP falling 2.35 2.55 2.75 V
VVDDP_UV_HYS VDDP undervoltage threshold hysterisis 75 mV
TSD Temperature shutdown 173 ℃
TSDH Temperature shutdown hysteresis 32 ℃
VVDDH_UV_R VDDH undervoltage threshold rising VDDH rising. 8.3 8.6 9.0 V
VVDDH_UV_F VDDH undervoltage threshold falling
TPSI3050-Q1 only.		 VDDH falling. 6.3 6.6 6.9 V
VVDDH_UV_F VDDH undervoltage threshold falling
TPSI3050S-Q1 only. One-shot enable mode only available in three-wire operation.		 VDDH falling. 7.2 7.5 7.8 V
VVDDH_UV_HYS VDDH undervoltage threshold hysterisis
TPSI3050-Q1 only.		 2 V
VVDDH_UV_HYS VDDH undervoltage threshold hysterisis
TPSI3050S-Q1 only.		 1.1 V
IQ_VDDH Internal quiescent current of VDDH supply. 36 µA
RDSON_VDRV Driver on resistance in low state Force VVDDH = 10 V,
sink IVDRV = 50 mA.		 1.7 Ω
Driver on resistance in high state Force VVDDH = 10 V,
source IVDRV = 50 mA.		 2.5 Ω
IVDRV_PEAK VDRV peak output current during rise VVDDH in steady state,
transition EN from low to high,
measure peak current.
 1.5 A
VDRV peak output current during fall VVDDH in steady state,
transition EN from high to low,
measure peak current.
 3 A
CMTI Common-mode transient immunity |VCM| = 1000 V 100 V/ns
TWO-WIRE MODE
VIH_EN Minimum voltage on EN to be detected as a valid logic high 6.5 V
VIL_EN Maximum voltage on EN to be detected as a valid logic low 2.0 V
IEN_START Enable current at startup EN = 0 V → 6.5 V 27 mA
IEN Enable current steady state EN = 6.5 V,
RPXFR = 7.32 kΩ,
RPXFR ≥100 kΩ or RPXFR ≤1 kΩ,
VVDDH in steady state.		 1.9 mA
EN = 6.5 V,
RPXFR = 20 kΩ,
VVDDH in steady state.		 6.8 mA
VVDDP_RIPPLE VDDP output voltage ripple EN = 6.5 V, VVDDH in steady state. 600 mV
VVDDH VDDH output voltage EN = 6.5 V,
VVDDH in steady state.		 9.4 10.2 11 V
VVDRV_H VDRV output voltage driven high EN = 6.5 V,
VVDDH in steady state,
no DC loading.		 9.4 10.2 11 V
VVDRV_L VDRV output voltage driven low EN = 6.5 V → 0 V,
VVDDH in steady state,
sink 10 mA load.		 0.1 V
VVDDM_IAUX Average VDDM voltage when sourcing external current EN = 6.5 V, steady state.
RPXFR = 7.32 kΩ,
RPXFR ≥ 100 kΩ or RPXFR ≤ 1 kΩ,
CDIV1 = CDIV2 = 220 nF,

source 0.4 mA from VDDM,
measure VDDM voltage.		 4.6 5.5 V
EN = 6.5 V, steady state.
RPXFR = 20 kΩ,
CDIV1 = CDIV2 = 220 nF,

source 1.7 mA from VDDM,
measure VDDM voltage.		 4.6 5.5 V
THREE-WIRE MODE
VIH_EN Minimum voltage on EN to be detected as a valid logic high.  VIH(min) = 0.7 x VVDDP
 		 VVDDP = 3 V 2.1 V
VVDDP = 5.5 V 3.85 V
VIL_EN Maximum voltage on EN to be detected as a valid logic low VVDDP = 3 V 0.9 V
VVDDP = 5.5 V 1.65 V
IVDDP VDDP average current in steady state EN = 3.3 V,
VVDDP = 3.3 V,
RPXFR = 7.32 kΩ,
RPXFR ≥ 100 kΩ or RPXFR ≤ 1 kΩ,
VVDDH in steady state,
measure IVDDP.		 3.1 mA
EN = 3.3 V,
VVDDP = 3.3 V,
RPXFR = 20 kΩ
VVDDH in steady state,
measure IVDDP.		 26
EN = 5 V,
VVDDP = 5 V,
RPXFR = 7.32 kΩ,
RPXFR ≥ 100 kΩ or RPXFR ≤ 1 kΩ,
VVDDH in steady state,
measure IVDDP.		 4.8 mA
EN = 5 V,
VVDDP = 5 V,
RPXFR = 20 kΩ,
VVDDH in steady state,
measure IVDDP.		 37 mA
VVDDM_IAUX Average VDDM voltage when sourcing external current VVDDP = 3.3 V, EN = 0 V, steady state,
RPXFR = 7.32 kΩ,
CDIV1 = CDIV2 = 220 nF,

source 0.4 mA from VDDM,
measure VVDDM.		 4.6 5.5 V
VVDDP = 5.0 V, EN = 0 V, steady state,
RPXFR = 7.32 kΩ,
CDIV1 = CDIV2 = 220 nF,

source 1.0 mA from VDDM,
measure VVDDM.		 4.6 5.5 V
VVDDP = 3.3 V, EN = 0 V, steady state,
RPXFR =20 kΩ,
CDIV1 = CDIV2 = 220 nF,

source 5.5 mA from VDDM,
measure VVDDM.		 4.6 5.5 V
VVDDP = 5.0 V, EN = 0 V, steady state,
RPXFR = 20 kΩ,
CDIV1 = CDIV2 = 220 nF,

source 10 mA from VDDM,
measure VVDDM.		 4.6 5.5 V
VVDDH VDDH output voltage VVDDP = 3.0 V,
EN = 3.0 V,
VVDDH in steady state.		 9.4 10.2 11 V
VVDRV_H VDRV output voltage driven high VVDDP = 3.0 V,
EN = 3.0 V,
VVDDH in steady state, no DC loading.		 9.4 10.2 11 V
VVDRV_L VDRV output voltage driven low VVDDP = 3.0 V,
EN = 0 V,
VVDDH in steady state,
VDRV sinking 10 mA.		 0.1 V

6.10 Switching Characteristics

over operating free-air temperature range (unless otherwise noted). Typicals at TA = 25℃. CVDDP = 220 nF, CDIV1 = CDIV2 = 3.3 nF, CVDRV = 100 pF, RPXFR = 7.32 kΩ ± 1%
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TWO-WIRE MODE
tLO_EN Low time of EN 5 µs
tLH_VDDH Propagation delay time from EN rising to VDDH at 50% level EN = 0 V → 6.5 V,  
VVDDH = 5.0 V.		 90 µs
tLH_VDRV Propagation delay time from EN rising to VDRV at 90% level EN = 0 V → 6.5 V,
VVDRV = 9.0 V.		 260 µs
tHL_VDRV Propagation delay time from EN falling to VDRV at 10% level EN = 6.5 V → 0 V,
VVDRV = 1.0 V.		 2.4 3 µs
tR_VDRV VDRV rise time from EN rising to VDRV from 15% to 85% level EN = 0 V → 6.5 V,
VVDRV = 1.5 V to 8.5 V.		 6 ns
tF_VDRV VDRV fall time from EN falling to VDRV from 85% to 15% level EN = 6.5 V → 0 V,
VVDRV = 8.5 V to 1.5 V.		 5 ns
THREE-WIRE MODE
tLO_EN Low time of EN VVDDP = 3.3 V, steady state. 5 µs
tHI_EN High time of EN VVDDP = 3.3V, steady state. 5 µs
tHI_VDRV High time of VDRV using one-shot enable.
TPSI3050S-Q1 only.
One-shot enable only available in three-wire mode.		 VVDDP = 3.3 V, steady state. 2.5 µs
tLH_VDDH Propagation delay time from VDDP rising to VDDH at 50% level EN = 0 V,
VVDDP =  0 V → 3.3 V at 1 V/µs,
VVDDH = 5.0 V.		 74 µs
tLH_VDRV Propagation delay time from EN rising to VDRV at 90% level VVDDP = 3.3 V,
VVDDH steady state,
EN =  0 V → 3.3 V,
VVDRV = 9.0 V.		 3 4.5 µs
tHL_VDRV Propagation delay time from EN falling to VDRV at 10% level VVDDP = 3.3 V,
VVDDH steady state,
EN =  3.3 V → 0 V, 
VVDRV = 1.0 V.		 2.5 3 µs
tHL_VDRV_PD Propagation delay time from VDDP falling to VDRV at 10% level.
Timeout mechanism due to loss of power on primary supply.		 EN = 3.3 V,
VVDDH steady state,
VVDDP =  3.3 V → 0 V at -1 V/µs,
VVDRV = 1.0 V.		 100 µs
tR_VDRV VDRV rise time from EN rising to VDRV from 15% to 85% level VVDDP = 3.3 V,
VVDDH steady state,
EN =  0 V → 3.3 V,
VVDRV = 1.5 V to 8.5 V.		 6 ns
tF_VDRV VDRV fall time from EN falling to VDRV from 85% to 15% level VVDDP = 3.3 V,
VVDDH steady state,
EN =  3.3 V → 0 V,
VVDRV = 8.5 V to 1.5 V.		 5 ns

6.11 Insulation Characteristic Curves

GUID-20211006-SS0I-Q1TJ-K8BV-VCSWGZZ4TGCP-low.svgFigure 6-1 Thermal Derating Curve for Limiting Current per VDE and IEC, Three-Wire Mode
GUID-20211006-SS0I-RCFD-4XCN-80FBTVQTKZMQ-low.svgFigure 6-3 Thermal Derating Curve for Limiting Power per VDE and IEC
GUID-20211006-SS0I-QJLH-NLV8-4NXKDSVKCW3B-low.svgFigure 6-2 Thermal Derating Curve for Limiting Current per VDE and IEC, Two-Wire Mode

6.12 Typical Characteristics

GUID-20211011-SS0I-MMWN-HNRF-XJXXJSHVT9LG-low.svg
Three-wire mode VDDP = 5.0 V RPXFR = 7.32 kΩ
CDIV1,2 = 3.3 nF CVDRV = 100 pF TA = 25°C
Figure 6-4 tLH_VDRV, Three-Wire Mode
GUID-20220912-SS0I-RZVH-SK1D-CZN9SP8JQJH0-low.svg
Three-wire mode VDDP = 3.3 V RPXFR = 7.32 kΩ
CDIV1 = 2.2 μF CDIV2 = 2.2 μF
Figure 6-6 tLH_VDRV versus CVDRV
GUID-20220916-SS0I-NKMT-QF4N-CDBV8Z5QFG86-low.svg
Two-wire mode EN = 12 V RPXFR = 7.32 kΩ
CDIV1 = 30 nF CVDRV = 100 pF TA = 25°C
CDIV2 = 100 nF
Figure 6-8 tLH_VDRV, Two-Wire Mode
GUID-20220916-SS0I-G3JW-29PC-GSGVLHV2NCWR-low.svg
tSTART represents the time from VDDP rising to VDDM and VDDH fully discharged rails reaching > 95% of their final levels.
Three-wire mode VDDP = 5.0 V TA = 25°C
IAUX = 0 mA
Figure 6-10 tSTART versus CDIV1, CDIV2
GUID-20220912-SS0I-S4GJ-SLJG-F660DZC9SV40-low.svg
Three-wire mode VDDP = 5.0 V TA = 25°C
Figure 6-12 Max. fEN versus QLOAD = 10 nC to 100 nC
GUID-20211008-SS0I-GHGC-M8FM-J7R7HN8QZ5QG-low.svg
Three-wire mode RPXFR = 20 kΩ TA = 25°C
CDIV1 = 470 nF CDIV2 = 470 nF CVDDP = 1 μF
Figure 6-14 VVDDM vs IAUX
GUID-20211011-SS0I-VFWM-G3TD-FFBH360WSV38-low.svg
Three-wire mode VDDP = 5.0 V RPXFR = 7.32 kΩ
CDIV1,2 = 3.3 nF CVDRV = 100 pF TA = 25°C
Figure 6-5 tHL_VDRV, Three-Wire Mode
GUID-20220912-SS0I-4SHZ-K9JX-VWXDGVTX42LC-low.svg
Three-wire mode VDDP = 3.3 V RPXFR = 7.32 kΩ
CDIV1 = 2.2 μF CDIV2 = 2.2 μF
Figure 6-7 tHL_VDRV versus CVDRV
GUID-20220916-SS0I-8QPV-ZDTD-46CS5PDGJGPH-low.svg
Two-wire mode EN = 12 V RPXFR = 7.32 kΩ
CDIV1 = 30 nF CVDRV = 100 pF TA = 25°C
CDIV2 = 100nF
Figure 6-9 tHL_VDRV, Two-Wire Mode
GUID-20220916-SS0I-VN4P-WNKW-FFZLXFZMTM1K-low.svg
tSTART represents the time from VDDP rising to VDDM and VDDH fully discharged rails reaching > 95% of their final levels.
Three-wire mode VDDP = 3.3 V TA = 25°C
IAUX = 0 mA
Figure 6-11 tSTART versus CDIV1, CDIV2
GUID-20220912-SS0I-MVXK-Z3WH-CX6CWJFM6DWS-low.svg
Three-wire mode VDDP = 5.0 V TA = 25°C
Figure 6-13 Max. fEN versus QLOAD = 100 nC to 1000 nC
GUID-20211008-SS0I-6KGX-FVCW-TSQ7F3RJF4GF-low.svg
Three-wire mode RPXFR = 11 kΩ TA = 25°C
CDIV1 = 470 nF CDIV2 = 470 nF CVDDP = 1 μF
Figure 6-15 VVDDM vs IAUX

 
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