外部高侧开关 MOSFET
外部反极性保护 MOSFET
LM74502/LM74502H 控制器与外部背对背连接的 N 沟道 MOSFET 配合工作，可实现低损耗反极性保护和负载断开的解决方案。该器件也可以配置为具有过压保护功能的负载开关，用于驱动高侧 MOSFET。3.2V 至 65V 的宽电源输入范围可实现对众多常用直流总线电压（例如，12V、24V 和 48V 输入系统）的控制。该器件可以承受并保护负载免受低至 -65V 的负电源电压的影响。LM74502/LM74502H 没有反向电流阻断功能，仅适用于进行输入反极性保护。
LM74502 控制器为外部 N 沟道 MOSFET 提供电荷泵栅极驱动。当使能引脚处于低电平时，控制器关闭，消耗大约 1µA 的电流，从而在进入睡眠模式时提供低系统电流。LM74502 和 LM74502H 还具有可编程的过压和欠压保护功能，可在发生故障时将负载从输入源切断。这些器件采用 2.9mm × 1.6mm 8 引脚 DDF 封装，额定工作温度范围为 –40°C 至 +125°C。
| 器件型号 | 封装 | 封装尺寸（标称值） |
|---|---|---|
| LM74502 | SOT-23 (8) | 2.90mm × 1.60mm |
| LM74502H |
| PIN | I/O(1) | DESCRIPTION | |
|---|---|---|---|
| NO. | NAME | ||
| 1 | EN/UVLO | I | EN/UVLO Input. Connect to VS pin for always ON operation. Can be driven externally from a micro controller I/O. Pulling the pin low below V(ENF) makes the device enter into low Iq shutdown mode. For UVLO, connect an external resistor ladder from input supply to EN/UVLO to ground. |
| 2 | GND | G | Ground pin |
| 3 | N.C | — | No connection |
| 4 | VCAP | O | Charge pump output. Connect to external charge pump capacitor. |
| 5 | VS | I | Input power supply pin to the controller. Connect a 100-nF capacitor across VS and GND pins. |
| 6 | GATE | O | Gate drive output. Connect to gate of the external N-channel MOSFET. |
| 7 | OV | I | Adjustable overvoltage threshold input. Connect a resistor ladder from input supply to OV pin to ground. When the voltage at OV pin exceeds the overvoltage cutoff threshold then the GATE is pulled low. GATE turns ON when the OV pin voltage goes below the OVP falling threshold. Connect OV pin to ground when OV feature is not used. |
| 8 | SRC | I | Source pin. Connect to common source point of external back-to-back connected N-channel MOSFETs or the source pin of the high side switch MOSFET. |
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Input Pins | VS to GND | –65 | 65 | V |
| EN/UVLO, OV to GND, V(VS) > 0 V | –0.3 | 65 | V | |
| EN/UVLO, OV, V(VS) ≤ 0 V | V(VS) | (65 + V(VS)) | ||
| SRC to GND, V(VS) ≤ 0 V | (V(VS) + 0.3) | V | ||
| SRC to GND, V(VS) > 0 V | –(70 – V(VS)) | V(VS) | V | |
| Output Pins | GATE to SRC | 0 | 15 | V |
| VCAP to VS | –0.3 | 15 | V | |
| Operating junction temperature(2) | –40 | 150 | °C | |
| Storage temperature, Tstg | –40 | 150 | °C | |
| VALUE | UNIT | ||||
|---|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±2000 | V | |
| Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins(2) | ±750 | ||||
| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| Input Pins | VS to GND | –60 | 60 | V | |
| EN/UVLO, OV, SRC to GND | –60 | 60 | |||
| External capacitance | VS | 22 | nF | ||
| VCAP to VS | 0.1 | µF | |||
| External MOSFET max VGS rating | GATE to SRC | 15 | V | ||
| TJ | Operating junction temperature range(2) | –40 | 150 | °C | |
| THERMAL METRIC(1) | LM74502 LM74502H |
UNIT | |
|---|---|---|---|
| DDF (SOT) | |||
| 8 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 133.8 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 72.6 | °C/W |
| RθJB | Junction-to-board thermal resistance | 54.5 | °C/W |
| ΨJT | Junction-to-top characterization parameter | 4.6 | °C/W |
| ΨJB | Junction-to-board characterization parameter | 54.2 | °C/W |
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| VS SUPPLY VOLTAGE | ||||||
| V(VS) | Operating input voltage | 4 | 60 | V | ||
| V (VS_POR) | VS POR Rising threshold | 3.9 | V | |||
| VS POR Falling threshold | 2.2 | 2.8 | 3.1 | V | ||
| V(VS POR(Hys)) | VS POR Hysteresis | 0.44 | 0.67 | V | ||
| I(SHDN) | Shutdown Supply Current | V(EN/UVLO) = 0 V | 0.9 | 1.5 | µA | |
| I(Q) | Operating Quiescent Current | IGND | 45 | 65 | µA | |
| I(REV) | VS pin leakage current during input reverse polarity | 0 V ≤ V(VS) ≤ – 65 V | 100 | 150 | µA | |
| ENABLE INPUT | ||||||
| V(EN_UVLOF) | Enable/UVLO falling threshold | 1.027 | 1.14 | 1.235 | V | |
| V(EN_UVLOR) | Enable/UVLO rising threshold | 1.16 | 1.24 | 1.32 | ||
| V(ENF) | Enable threshold voltage for low IQ shutdown | 0.32 | 0.64 | 0.94 | V | |
| V(EN_Hys) | Enable Hysteresis | 38 | 90 | 132 | mV | |
| I(EN/UVLO) | Enable sink current | V(EN/UVLO) = 12 V | 3 | 5 | µA | |
| GATE DRIVE | ||||||
| I(GATE) | Peak source current | V(GATE) – V(SRC) = 5 V | 40 | 60 | 77 | µA |
| I(GATE) | Peak source current | V(GATE) – V(SRC) = 5 V, LM74502H | 3 | 11 | mA | |
| Peak sink current | EN= High to Low V(GATE) – V(SRC) = 5 V |
2370 | mA | |||
| RDSON | discharge switch RDSON | EN = High to Low V(GATE) – V(SRC) = 100 mV |
0.4 | 2 | Ω | |
| CHARGE PUMP | ||||||
| I(VCAP) | Charge Pump source current (Charge pump on) | V(VCAP) – V(VS) = 7 V | 162 | 300 | 600 | µA |
| Charge Pump sink current (Charge pump off) | V(VCAP) – V(VS) = 14 V | 5 | 10 | µA | ||
| V(VCAP) – V(VS) | Charge pump voltage at V(VS) = 3.2 V | I(VCAP) ≤ 30 µA | 8 | V | ||
| V(VCAP) – V(VS) | Charge pump turn on voltage | 10.3 | 11.6 | 13 | V | |
| V(VCAP) – V(VS) | Charge pump turn off voltage | 11 | 12.4 | 13.9 | V | |
| V(VCAP) – V(VS) | Charge Pump Enable comparator Hysteresis | 0.45 | 0.8 | 1.25 | V | |
| V(VCAP UVLO) | V(VCAP) – V(S) UV release at rising edge | 5.7 | 6.5 | 7.5 | V | |
| V(VCAP UVLO) | V(VCAP) – V(S) UV threshold at falling edge | 5.05 | 5.4 | 6.2 | V | |
| OVERVOLTAGE PROTECTION | ||||||
| V(OVR) | Overvoltage threshold input, rising |
1.165 | 1.25 | 1.333 | V | |
| V(OVF) | Overvoltage threshold input, falling |
1.063 | 1.143 | 1.222 | V | |
| V(OV_Hys) | OV Hysteresis | 100 | mV | |||
| I(OV) | OV Input leakage current | 0 V < V(OV) < 5 V | 12 | 50 | 110 | nA |
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| ENTDLY | EN high to Gate Turn On delay | V(VCAP) > V(VCAP UVLOR), V(EN/UVLO) > V(EN_UVLOR) to V(GATE-SRC) > 5 V, C(GATE-SRC) = 4.7 nF LM74502H | 75 | 110 | µs | |
| tUVLO_OFF(deg)_GATE | GATE Turnoff delay during EN/UVLO | V(EN/UVLO) ↓ to V(GATE-SRC) < 1 V, C(GATE-SRC) = 4.7 nF | 2 | µs | ||
| tOVP_OFF(deg)_GATE | GATE Turnoff delay during OV | V(OV) ↑ to V(GATE-SRC) < 1 V, C(GATE-SRC) = 4.7 nF | 0.6 | 1 | µs | |
| tOVP_ON(deg)_GATE | GATE Turnon delay during OV | V(OV) ↓ to V(GATE-SRC) > 5 V, C(GATE-SRC) = 4.7 nF LM74502H |
5 | 10 | µs | |
The LM74502 and LM74502H controller has all the features necessary to implement an efficient and fast reverse polarity protection circuit with load disconnect feature. This easy to use reverse polarity protection controller is paired with an external back-to-back connected N-channel MOSFETs to replace other reverse polarity schemes such as a P-channel MOSFETs. The wide input supply range of 4 V to 65 V allows protection and control of 12-V and 24-V input supply systems. The device can withstand and protect the loads from negative supply voltages down to –65 V. An integrated charge pump drives external back-to-back connected N-channel MOSFETs with gate drive voltage of approximately 13 V. LM74502 with its 60-μA peak gate drive strength is suitable for applications that needs inherent inrush current control. LM74502H with its fast gate drive strength of 11-mA peak is suitable for applications which need fast turn-on and turn-off of external MOSFET switch. LM74502 features an adjustable overvoltage protection using the OV pin. with the enable pin low during the standby mode, both the external MOSFETs and controller is off and draws a very low shutdown current of 1 μA.
The VS pin is used to power the LM74502's internal circuitry, typically drawing 45 µA when enabled and 1 µA when disabled. If the VS pin voltage is greater than the POR Rising threshold, then LM74502 operates in either shutdown mode or conduction mode in accordance with the EN/UVLO pin voltage. The voltage from VS to GND is designed to vary from 65 V to –65 V, allowing the LM74502 to withstand negative voltage transients.
where
To remove any chatter on the gate drive approximately 800 mV of hysteresis is added to the VCAP undervoltage lockout. The charge pump remains enabled until the VCAP to VS voltage reaches 12.4 V, typically, at which point the charge pump is disabled decreasing the current draw on the VS pin. The charge pump remains disabled until the VCAP to VS voltage is below to 11.6 V typically at which point the charge pump is enabled. The voltage between VCAP and VS continue to charge and discharge between 11.6 V and 12.4 V as shown in Figure 8-1. By enabling and disabling the charge pump, the operating quiescent current of the LM74502 is reduced. When the charge pump is disabled it sinks 5-µA typical.
The gate driver is used to control the external N-Channel MOSFET by setting the appropriate GATE to SRC voltage.
Before the gate driver is enabled, the following three conditions must be achieved:
The controller offers two gate drive variants. LM74502 with typical peak gate drive strength of 60 μA is suitable to achieve smooth start-up with inherent inrush current control due to its lower gate drive strength.
LM74502H with its 11 -mA typical peak gate drive strength is suitable for applications which need faster turn on such as load switch applications.
LM74502, LM74502H SRC pin is capable of handling negative voltage which also makes it suitable for load disconnect switch applications with loads which are inductive in nature.
An external circuit as shown in Figure 8-2 can be added on the GATE pin of the LM74502 to have additional inrush current control for the applications which have large capacitive loads.
The CdVdT capacitor is required for slowing down the GATE voltage ramp during power up for inrush current limiting. Use Equation 3 to calculate CdVdT capacitance value.
where IGATE is 60 μA (typical), IINRUSH is the inrush current and COUT is the output load capacitance. An extra resistor, RG, in series with the CdVdT capacitor acts as an isolation resistor between Cdvdt and gate of the MOSFET.
The inrush current control scheme shown in Figure 8-2 is not applicable to LM74502H as its gate drive is optimized for fast turn-on load switch applications.
The LM74502 has an enable pin, EN/UVLO. The enable pin allows for the gate driver to be either enabled or disabled by an external signal. If the EN/UVLO pin voltage is greater than the rising threshold, the gate driver and charge pump operates as described in the Gate Driver (GATE, SRC) and Charge Pump (VCAP) sections. If the enable pin voltage is less than the input low threshold, the charge pump and gate driver are disabled placing the LM74502 in shutdown mode. The EN/UVLO pin can withstand a voltage as large as 65 V and as low as –65 V. This feature allows for the EN/UVLO pin to be connected directly to the VS pin if enable functionality is not needed. In conditions where EN/UVLO is left floating, the internal sink current of 3 uA pulls EN/UVLO pin low and disables the device.
An external resistor divider connected from input to EN/UVLO to ground can be used to implement the input Undervoltage Lockout (UVLO) functionality in the system. When EN/UVLO pin voltage is lower than UVLO comparator falling threshold (VEN/UVLOR) but higher than enable falling threshold (VENF), the device disables gate drive voltage, however, charge pump is kept on. This action ensures quick recovery of gate drive when UVLO condition is removed. If UVLO functionality is not required, connect EN/UVLO pin to VS.